Concurrent Technologies VP 110/01 Series, Technical Reference Manual

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5.2 VME Byte Swapping
The VP 110/01x provides hardware that performs fast byte swapping for aligned D16, D32 and
D64 VME transfers. Byte swapping can be enabled separately for master and slave transfers
under software control, using Status & Control Register 0 (see Section 9.1 for further details).
Swapping is performed as follows:-
D16 (Double Byte 2 - 3):
D[31...24] < - > D[23...16]
D[23...16] < - > D[31...24
D16 (Double Byte 0 - 1):
D[15....8] < - > D[7.....0]
D[7.....0] < - > D[15....8]
D32 (Quad Byte 0 - 3):
D[31...24] < - > D[7....0]
D[23...16] < - > D[15....8]
D[15....8] < - > D[23...16]
D[7.....0] < - > D[31...24]
D64 (Octal Byte 0 - 7):
D[63...56] < - > D[39...32]
D[55...48] < - > D[47...40]
D[47...40] < - > D[55...48]
D[39...32] < - > D[63...56]
D[31...24] < - > D[7.....0]
D[23...16] < - > D[15....8]
D[15....8] < - > D[23...16]
D[7.....0] < - > D[31...24]
The hardware decodes the VME transfer taking place to see if it is swappable, checks to see if
swapping is enabled and then configures a set of multiplexors to perform the required data
swap. For master and slave read cycles the byte swap hardware imposes negligible delay on
the VME bus cycle since the decode and configuration occur before the data is valid. For write
cycles the hardware imposes an approximate delay of 50ns in order to provide the required
setup time before the data strobes are asserted. The delay applies to single cycle transfers and
the first cycle of block transfers.
NOTE The delay can be turned off under software control, but only if the user can
guarantee that only swappable cycles will be run across the VME interface.
5-2 VP 110/01x
VME Interface