Concurrent Technologies VP 110/01 Series, Technical Reference Manual

Page: 68 / 150

8.4.2 Watchdog Configuration
The watchdog circuitry contains features to safeguard against accidental use through faulty or
unintended software actions. To enable the watchdog the following sequence of events needs
to be performed.
1) Read the watchdog register. Check the status of the watchdog enable jumper (bit 4). If it
reads ‘low’ then proceed to step 2. If it reads ‘high’ then the watchdog cannot be enabled in
software.
2) Set bits 1 & 0 to the complement of each other (i.e. 0,1 or 1,0) and at the same time set bit
5 ‘high’.
3) Write the new value back.
4) Complement bits 1 & 0. Write the new value to the watchdog register
5) Repeat step 4.
Once the watchdog has been enabled, it can be disabled by repeating the above procedure with
bit 5 set ‘low’.
8.4.3 Using the Watchdog
Once enabled, the watchdog timer must be restarted at regular intervals to prevent it expiring.
The maximum interval is pre-set to 1 second. This is a function of the watchdog chip and cannot
be changed. If the watchdog timer is not restarted within this time it will time out and cause a
reset or NMI depending on the state of bit 2 of the Watchdog Status & Control register. To
restart the watchdog the complement of the lower two bits needs to be written into the Watchdog
Status & Control register. These two bits must also be the complement of each other i.e. 0,1 or
1,0. Writing any other value or the same value will not restart the watchdog.
If the watchdog time-out is configured to generate a board reset and a time-out occurs the
watchdog circuit will also be reset. The watchdog must be enabled to be re-enabled after a reset
has occurred. This has been done to allow operating systems software to boot after a reset
without having to keep the watchdog from timing out during this period. The watchdog status bit
will not be cleared; this must to be done by enabling and restarting the watchdog. The reason
for this is to preserve the status of the watchdog timeout to allow software to determine the
source of an NMI or if a reset was caused by the watchdog.
NOTE Once an erroneous value has been written into the watchdog register it will take
two further writes using the correct values to restart the watchdog again.
Therefore, when changing any bit in the register when the watchdog has been
enabled, bits 1 & 0 should be complemented.
NOTE The actual time-out of the watchdog chip can vary between 1s and 2.25s. To
guarantee correct operation on all boards the restart interval should be less than
1s.
8-8 VP 110/01x
Additional Local I/O Functions