Concurrent Technologies VP 110/01 Series, Technical Reference Manual

Page: 46 / 150

5.4.1 VME Address Capture Read Register (Read Only)
7 6 5 4 3 2 1 0
|________|________|_________|________|_________|_________|_________|_________|
| | | | | | | |
CAPTURE RFU RFU RFU SD3 SD2 SD1 SD0
STATUS
Bit 3-0: Captured Address
The VME address is sequentially read as follows following a captured bus error event.
SD3 SD2 SD1 SD0 Read Cycle
A31 A30 A29 A28 1
A27 A26 A25 A24 2
A23 A22 A21 A20 3
A19 A18 A17 A16 4
A15 A14 A13 A12 5
A11 A10 A09 A08 6
A07 A06 A05 A04 7
A03 A02 A01 LWORD 8
DS1 DS0 AM05 AM04 9
AM03 AM02 AM01 AM00 10
WR XX XX XX 11
XX XX XX XX 12
XX XX XX XX 13
XX XX XX XX 14
XX XX XX XX 15
XX XX XX XX 16
Table 5-1 VME Address Capture Read Register
The sequence will repeat for subsequent read accesses and is only readable after a bus error
address capture.
The sequence will repeat for subsequent read accesses and is only readable after a bus error
address capture.
Bits A31 - A01 form the most significant 31 bits of the address which caused the bus error. All
these bits are valid even for A24 or A16 bus cycles. Bits DS0 and DS1 indicate the state of the
high and low byte enables on the VME bus. In conjunction with the LWORD bit these bits
identify which of the four byte lanes of the VME data bus were used in the faulty cycle.
Bits AM05 to AM00 form the address modifier code and are decoded as shown in Table 5-2.
Bits 6-4: Reserved
Bit 7: Capture Status
0 = idle
1 = capture in progress
5-4 VP 110/01x
VME Interface