PXIe Platform Bit Error Rate Tester
|
BERTPXIe-1003/1005
Coherent Solutions Ltd.
Version
1.00
31
N
OTE
When the system is busy, you cannot use some features. For example,
when the system is busy doing error detection or eye scan, you cannot
change the pattern generation settings.
Module configuration
Before starting to use the BERTPXIe modules to do error detection or pattern generation,
configure the modules appropriately.
8.1.1
Set up the data rate
Each BERTPXIe module has an integrated, low noise, fractional clock synthesizer, which can
set the relevant frequency based on the data rate that you set. For your convenience, a list of
commonly used data rates has been programmed and stored inside the module, with the
relative frequency calibration files for optimal frequency accuracy and lowest RMS clock jitter.
To specify the standard data rate, click the STANDARD DATA RATE drop-down list in the
upper-left corner of the page and then select an appropriate data rate value.
To specify an arbitrary data rate for pattern generation or error detection, type an appropriate
value in the ARBITARY DATA RATE OF PPG or the ARBITARY DATA RATE OF ED box. In this
case, the value of the STANDARD DATA RATE box automatically changes to
<ARBITARY>
, as
shown below. You can also use the up or down arrows to the right of the value to increase or
decrease the value.
Each time when the data rate is changed, the clock synthesizer is unlocked for the frequency
to change and then locked once the frequency is set. The lock status is indicated by the
SYNTHESIZER VCO LOCK indicator on the CLOCK tab, as shown below:
