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TS9000/TS9050 TouchStar Systems User Manual
TABLE 12 - DMA CHANNEL ASSIGNMENTS
Channel
I/O Address
Description
DMA0
000H - 00FH
DMA Controller
DMA1
0C0H - ODFH
I/O addresses 080H - 08FH are occupied by
the DMA page registers
DMA2
Floppy Disk Controller
DMA3
AMD Ethernet Adapter (Windows 3.X, DOS)
DMA4
DMA Access Controller
DMA5
Unused
DMA6
Unused
DMA7
Unused
Programmable Interval Timer
The programmable interval timer is equivalent to the Intel 8254,
and occupies I/O addresses 0040
H
through 0043
H
. This general
purpose counter/timer generates accurate time delays under
software control.
Counter/Timer Circuit
The counter control circuit (CCC) contains three independently
operating, 16-bit counters driven by a common 1.19MHz clock.
Each counter counts in binary or binary-coded decimal (BCD).
Each can be programmed for operation as either a counter or
timer. Common control logic decodes the information written to
the counter control circuit to load, read, configure, and control
each timer.
Counter 0 connects to IRQ0 of the internal interrupt controller
for system time-keeping and task-switching.
Counter 1 generates pulses for the DRAM refresh generator.
Counter 2 is used as an interval time, counter, or gated rate/
pulse generator. Counter 2 output can be used as an audio
speaker tone generator.
Each counter can be programmed to operate in any of the six
modes shown in Table 13. It should be noted that modes 1 and 5
do not have external hardware trigger signals.
B - SYSTEM REFERENCE
