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TS9000/TS9050 TouchStar Systems User Manual
TABLE 11 - HARDWARE INTERRUPTS
Interrupt
Level Function
IRQ0
08H
Counter/Timer (18.2 fps)
IRQ1
09H
Keyboard
IRQ2
0AH
Slaved from IRQ8 - IRQ15
IRQ3
0BH
COM2/COM4
IRQ4
0CH
COM1/COM3
IRQ5
0DH
Unassigned
IRQ6
0EH Unassigned
IRQ7
0FH Parallel
port
IRQ8
70H
Real-time clock (RTC)
IRQ9
71H
Touchscreen, slaved to IRQ2 in software
IRQ10
72H
Unassigned
IRQ11
73H
Mouse
IRQ12
74H
Unassigned
IRQ13
75H Coprocessor
IRQ14
76H Fixed
disk
IRQ15
77H Unassigned
DMA Controller
The direct memory access (DMA) controller handles requests
for input/output activity that can transfer data without inter-
vention from the CPU. This allows data transfers to occur at a
5 to 10MB per second rate.
Each of the two controllers is a four-channel DMA device that
can generate the memory addresses and control signals neces-
sary to transfer information directly between a peripheral
device and memory. The two DMA controllers are internally
cascaded to provide four DMA channels for transfers to 8-bit
peripherals (DMA1), and three channels for transfers to 16-bit
peripherals (DMA2). Table 12 provides a summary of the DMA
channel assignments.
SYSTEM REFERENCE - B
