CAEN
Electronic Instrumentation
UM3148
–
DT5730/DT5725 User Manual rev. 2
6
1
Introduction
The DT5730 is a Desktop module housing a 8-channel 14-bit 500 MS/s FLASH ADC Waveform Digitizer with software
selectable 2 V
pp
or 0.5 V
pp
input dynamic range on single ended MCX coaxial connectors. The DC offset is adjustable in
the ±1 V (@ 2 V
pp
) or ±0.25 (@ 0.5 V
pp
) range via a 16-bit DAC on each channel (see §
Analog Input Stage
).
Operationally, the mod. DT5725 differs from the DT5730 for working at 250 MS/s sampling frequency.
The ADC resolution and the sampling frequency make these digitizers well suited for mid-fast signal detection systems
(e.g. liquid or inorganic scintillators coupled to PMTs or Silicon Photomultipliers).
Each channel has a SRAM Multi-Event Buffer divisible into 1 ÷ 1024 buffers of programmable size. Two sizes of the
channel digital memory are available by ordering option (see
Tab. 1.1
).
DT5730 and DT5725 digitizers are provided with FPGAs that can run special DPP firmware for Physics Applications (see
§
13
).
A common acquisition trigger signal can be fed externally via the front panel TRG-IN input connector or via software.
Alternatively, each channel is able to generate a self-trigger when the input signal goes under/over a programmable
threshold. For each couple of adjacent channels, the relevant self-triggers are then processed to provide out a single
trigger request. In the DPP firmware, the trigger requests can be used at channel level for the event acquisition
(independent triggering), while in the default firmware they can be processed by the board to generate a common
trigger causing all the channels to acquire an event simultaneously. The trigger from one board can be propagated to
the other boards through the front panel GPO output connector.
During the acquisition, the data stream is continuously written in a circular memory buffer. When the trigger occurs,
the digitizer writes further samples for the post trigger and freezes the buffer that can be read by one of the provided
readout links. The acquisition can continue without any dead time in a new buffer.
DT5730 and DT5725 feature front panel CLK-IN connector as well as an internal PLL for clock synthesis from
internal/external references. Multi-board synchronization is supported, so all DT5730 or all DT5725 can be
synchronized to a common clock source and ensuring Trigger time stamps alignment. The fan-in of an external clock
signal to each CLK-IN is required. Once synchronized, all data will be aligned and coherent across the multi-board
system.
Each module houses USB 2.0 and Optical Link interfaces. USB 2.0 allows data transfers up to 30 MB/s. The Optical Link
(CAEN proprietary CONET protocol) supports transfer rate of 80 MB/s and offers Daisy chain capability. Therefore, it is
possible to connect up to 8 ADC modules to a single A2818 Optical Link Controller, or up to 32 using a A3818 (4-link
version). Optical Link and USB accesses are internally arbitrated.