CAEN
Electronic Instrumentation
UM3148
–
DT5730/DT5725 User Manual rev. 2
31
Acquisition Synchronization
Each channel of the digitizer is provided with a SRAM memory that can be organized in a programmable number N
b
of
circular buffers (N
b
= [1:1024], see
Tab. 9.1
). When the trigger occurs, the FPGA writes further a programmable number
of samples for the post-trigger and freezes the buffer, so that the stored data can be read via USB or Optical Link. The
acquisition can continue without dead-time in a new buffer.
When all buffers are filled, the board is considered FULL: no trigger is accepted and the acquisition stops (i.e. the
samples coming from the ADC are not written into the memory, so they are lost). As soon as at least one buffer is read
out, the board exits the FULL condition and acquisition restarts.
Note:
When the acquisition restarts, no trigger is accepted until at least the entire buffer is written. This means that
the dead time is extended for a certain time (depending on the size of the acquisition window) after the board exits
the FULL condition.
A way to eliminate this extra dead time is by setting bit[5] = 1 at register address 0x8100. The board is so programmed
to enter the FULL condition when N-1 buffers are written: no trigger is then accepted, but samples writing continues in
the last available buffer. As soon as one buffer is readout and becomes free, the boards exits the FULL condition and
can immediately accept a new trigger. This way, the FULL reflects the BUSY condition of the board (i.e. inability to
accept triggers); if required, the BUSY signal can be provided out on the digitizer front panel through the GPO LEMO
connector (bit[20], bits[19:18] and bits[17:16] at register address 0x811C).
Note:
when bit[5] = 1, the minimum number of circular buffers to be programmed is N = 2.
In some cases, the BUSY propagation from the digitizer to other parts of the system has some latency and it can
happen that one or more triggers occur while the digitizer is already FULL and unable to accept those triggers. This
condition causes event loss and it is particularly unsuitable when there are multiple digitizers running synchronously,
because the triggers accepted by one board and not by other boards cause event misalignment.
In this cases, it is possible to program the BUSY signal to be asserted when the digitizer is close to FULL condition, but it
has still some free buffers (Almost FULL condition). In this mode, the digitizer remains able to accept some more
triggers even after the BUSY assertion and the system can tolerate a delay in the inhibit of the trigger generation.
When the Almost FULL condition is enabled by setting the Almost FULL level (register address 0x816C) to X, the BUSY
signal is asserted as soon as X buffers are filled, although the board still goes FULL (and rejects triggers) when the
number of filled buffers is N or N-1, depending on bit[5] at register address 0x8100 as described above.
It is possible to provide the BUSY signal on the digitizer front panel GPO output (bit[20], bits[19:18] and bits[17:16] at
register address 0x811C are involved).