CAEN
Electronic Instrumentation
UM6508
–
DT5495 User Manual rev. 0
37
MFPGA Firmware Revision Register
Bit
Description
[31:16]
reserved
[15:8]
Major revision number
[7:0]
Minor revision number
Software Reset Register
Bit
Description
[31:0]
The value written into this register will determine the kind of software
reset:
1 = generate a local bus reset only (nLBRES local bus signal)
Others = reserved for future options
Scratch Register
Bit
Description
[31:0]
This register allows to perform 32-bit accesses for test purposes. Default
value is 0xAAAAAAAA
Flash Configuration (0x8500-0x8AFF)
This address range is reserved to flash remote programming.
Note:
access to the FLASH is through the provided functions of the PLULib library (see Sect.
Software Tools
)
.
Internal Scratch SRAM(0x8C00-0x8FFF)
This area is available either for test access or for volatile data storage. Any address in this interval is implemented by an
internal RAM location.
