CAEN
Electronic Instrumentation
UM6508
–
DT5495 User Manual rev. 0
57
➢
CLOCK FREQUENCY register:
Sets the value of the frequency divider factor of the clock selectable as input (0x0 = 50
MHz, 0x1= 25 MHz, ….).
Address:
0x1804.
Mode:
Read and Write.
Bit
Description
[31:0]
Frequency divider factor
0x0 = Clock frequency is 50 MHz
0x1 = Clock frequency is 25 MHz
…
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DATA WRITE register:
The information written in this register is sent to the GDG.
Address:
0x7F00.
Mode:
Read and Write.
Bit
Description
[31:0]
Data
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COMMAND register
Address:
0x7F04.
Mode:
Read and Write.
Bit
Description
[31:16]
reserved
[15:12]
Control register[0]=1:
0x2 = The content of the Data write register is written in the gate internal buffer
0x3 = The content of the Data write register is written in the delay internal buffer
Control register[1]=1:
0x2 = The gate value of the channel specified by [7:0] is read
0x3 = The delay value of the channel specified by [7:0] is read
[11:8]
0x1 = The values of gate and delay previously buffered using [15:12] are sent to the
DFPGA for the channel specified by [7:0]
0x3 = The delays are reset
0x4 = The delays are calibrated
0x5 = The values of gate and delay previously buffered using [15:12] are broadcast to all
channels
[7:0]
Delay channel selection (the 3 MSBs should be set to 0)
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CONTROL register
Address:
0x7F08.
Mode:
Read and Write.
Bit
Description
[30:2]
reserved
[1]
1 = Start of read operation
[0]
1 = Start of write operation
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DATA READ register:
The information from the DFPGA can be read in this register.
Address:
0x7F0C.
Mode:
Read only.
Bit
Description
[31:0]
Data
