CAEN
Electronic Instrumentation
UM6508
–
DT5495 User Manual rev. 0
40
In case the A395D mezzanine is used, the mapping between the external channels and the X bus is shown in
Tab. 10.5
. A schematic view of the A395D board is shown in
Fig. 10.1
.
CHANNEL
INPUT SIGNALS
OUTPUT SIGNALS
0
X[2]
X[0]
1
X[18]
X[16]
2
X[3]
X[1]
3
X[19]
X[17]
4
X[14]
X[12]
5
X[30]
X[28]
6
X[15]
X[13]
7
X[31]
X[29]
Tab. 10.5:
A395D mapping
Fig. 10.1:
CAENComm Demo Java and LabVIEW graphical interface
For example:
•
A395D channel 0 can be driven with signal X[0] and its status can be read from X[2].
•
A395D channel 1 can be driven with signal X[16] and its status can be read from X[18].
➢
User LEDs:
Refer to the eight User LEDs on the front panel (see Chap.
4
).
SIGNAL NAME
WIDTH
TYPE
DESCRIPTION
LED
8
Output LED drivers
Tab. 10.6:
LED ports description table
In order to switch on one of the eight LEDs on the front panel, the corresponding signal (LED[7:0]) should be set to 1.
➢
Gate & Delay Generator interface ports:
The GDG is connected to the UFPGA via the following signals:
SIGNAL NAME
WIDTH
TYPE
DESCRIPTION
GD_START
32
Output GDG start signals
GD_DELAYED
32
Input
GDG output signals
SPI_MISO
1
Input
SPI MISO (Master Input Slave Output)
SPI_SCLK
1
Output Serial clock
SPI_CS
1
Output SPI Chip Select
SPI_MOSI
1
Output SPI MOSI (Master Output Slave Input)
Tab. 10.7:
Gate and Delay Generator ports description table