CAEN
Electronic Instrumentation
UM6508
–
DT5495 User Manual rev. 0
56
11.7
Gate and Delay Demo Description
Introduction
In this demo the functionalities and use of the Gate and Delay Generator will be shown. The signal to be delayed can be
selected between an internally-generated clock of configurable frequency (submultiples of 50 MHz) and the input from
the G0 connector (please refer to Sect.
Gate and Delay Controller
for the G0 and G1 port configuration required in this
case). An output signal of configurable width and delay with respect to the input signal’s leading edge will be available
on G1.
Register Map
In this example, 3 registers are used, 1 of which (MONITOR register) can be only read and 2 (CONTROL registers) can be
both read and written. All registers are 32-bit wide and can be accessed in single access mode
.
ADDRESS
REGISTER/CONTENT
ACCESS MODE
Read/Write
0x1000
0x1800
0x1804
Firmware Version
Control register
Clock frequency register
A24/A32
A24/A32
A24/A32
D16/D32
D16/D32
D16/D32
R
R/W
R/W
The registers of the Gate and Delay controller are used to configure the GDG parameters.
ADDRESS
REGISTER/CONTENT
ACCESS MODE
Read/Write
0x7F00
0x7F04
0x7F08
0x7F0C
0x7F10
Data write register
Command register
Control register
Data read register
Status register
A24/A32
A24/A32
A24/A32
A24/A32
A24/A32
D16/D32
D16/D32
D16/D32
D16/D32
D16/D32
R/W
R/W
R/W
R
R
Register Description
➢
FIRMWARE VERSION register:
Stores the revision number of the firmware.
Address:
0x1000.
Mode:
Read only.
Bit
Description
[31:0]
Revision Number
➢
CONTROL register:
Address:
0x1800.
Mode:
Read and Write.
Bit
Description
[8:4]
The DFPGA channel used to delay the input signal
[1]
Input signal selection:
0 = clock signal (frequency set by bits [8:4]
1 = G0 input
[0]
I/O port level selection:
0 = NIM level
1 = TTL level
WARNING:
When the G0 connector is used as an input, the user should follow the procedure described in Sect.
User FPGA I/O ports
.
