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CAEN

Electronic Instrumentation

UM6508

–

DT5495 User Manual rev. 0

Software Development

Software applications can be developed for the DT5495 by using the functions and features provided by the CAEN
PLULib library

[RD3]

CAEN PLULib library requires the Main FPGA Application Firmware revision 1.4 or higher!

Summary of Contents for DT5495

Page 1: ...CAEN Tools for Discovery n Electronic Instrumentation User Manual UM6508 DT5495 Desktop Programmable Logic Unit Rev 0 August 2nd 2018...

Page 2: ...thernet Interface FPGA Field Programmable Gate Array GDG Gate and Delay Generator LB Local Bus LBM Local Bus Master LBS Local Bus Slave LED Light Emitting Diode MFPGA Main FPGA SPI Serial Peripheral I...

Page 3: ...umed for inaccuracies CAEN SpA reserves the right to modify its products specifications without giving any notice for up to date information please visit www caen it MADE IN ITALY We stress the fact t...

Page 4: ...Front Panel Connector Cabling 22 7 4 Power on Configuration Sequence 23 Restore Function 23 8 Communication 24 8 1 Drivers 24 Direct USB Driver Installation 24 8 2 Ethernet Configuration 28 8 3 Web In...

Page 5: ...al installation Step2 25 Fig 8 4 USB driver manual installation Step3 26 Fig 8 5 USB driver manual installation Step4 26 Fig 8 6 USB driver manual installation Step5 27 Fig 8 7 The Network and Sharing...

Page 6: ...of the DT5495 36 Tab 9 3 CSR registers 36 Tab 10 1 Clock ports description table 39 Tab 10 2 Mainboard Robinson Nugent connector description table 39 Tab 10 3 LEMO G ports description table 39 Tab 10...

Page 7: ...cated JTAG connector allows for in system JTAG configuration and debugging e g using Altera SignalTap Simple operations like retrieving the board information or changing the ethernet settings can be p...

Page 8: ...95SC Channel Latching Scaler for V2495 and DT5495 WFW2495SCXAA Accessories Description Product Code A395A 32 LVDS ECL PECL input channels WA395XAAAAAA A395B 32 LVDS output channels WA395XBAAAAA A395C...

Page 9: ...trumentation UM6508 DT5495 User Manual rev 0 9 2 Block Diagram A B C 32 32 32 32 32 32 USER PROGRAMMABLE FPGA UFPGA MAIN FPGA MFPGA 16 bit ETHERNET LOCAL BUS G Gate and Delay Generator D E F USB 32 Fi...

Page 10: ...PGA Cyclone V GX Main FPGA Cyclone V E Gate and Delay Generator Local Bus 16 bit 50MHz USB PHY FLASH FLASH FLASH A PORT IN D PORT IN OUT B PORT IN E PORT IN OUT C PORT OUT F PORT IN OUT USB G PORT IN...

Page 11: ...rnal flash memory can store a set of firmware images to be loaded on the User FPGA A dedicated JTAG connector allows to program the UFPGA on the fly for fast firmware prototyping and debugging 3 5 Gat...

Page 12: ...ACTIVITY LED CONFIGURATION LED A CONNECTOR 32 ch input only USER CONFIGURATION LEDs B CONNECTOR 32 ch input only C CONNECTOR 32 ch output only G0 G1 CONNECTORS Input Output selectable ETH PORT JTAG CO...

Page 13: ...RNET PORT FUNCTION Ethernet connector to communicate with the DT5495 for board configuration and firmware upgrade ELECTRICAL SPECS 10 100T ETHERNET MECHANICAL SPECS Series RJ45 connectors Type GIGABIT...

Page 14: ...t high impedance state External 50 termination required when using the connector as input ELECTRICAL SPECS See Tab 5 1 MECHANICAL SPECS Series 00 LEMO Connectors Type EPY 00 250 NTN Manufacturer LEMO...

Page 15: ...ECS Series 4600 panel rectangular connectors Type 4610 6350 Manufacturer 3M RESTORE BUTTON FUNCTION Restores the default IP address and forces the module in factory state see Sect Restore Function ELE...

Page 16: ...umentation UM6508 DT5495 User Manual rev 0 16 ON OFF SWITCH FUNCTION Power switch of the module on I off O ELECTRICAL SPECS N A MECHANICAL SPECS Series Power Switches Type Rocker SwitchP A11131121000...

Page 17: ...ed when used as input Logic TTL IN Direct TTL OUT Direct NIM IN Invert NIM OUT Direct Signal Single ended NIM TTL selectable Bandwidth 250 MHz Front Panel Connector LEMO 00 GATE and DELAY GENERATOR Mi...

Page 18: ...P1 SR1 TG type 34 34 pins POWER CONSUMPTIONS 1 4 A max 5V internal rail 12V and 12V internal rails are not used Tab 5 4 A395C Mezzanine specifications table A395D Mezzanine Board I O SECTION Nr of Ch...

Page 19: ...anual rev 0 19 6 Power Requirements The DT5495 is powered by the external 45W 12V AC DC stabilized power supply unit included in the delivered kit see Sect Shipping Content The maximum required curren...

Page 20: ...with DT5495 7 1 Shipping Content DESCRIPTION ITEM DT5495 Programmable VME Logic Unit With or without mezzanine board extension s according to the order USB cable Ethernet cable Power Supply adaptor D...

Page 21: ...rev 0 21 7 2 Mezzanine Boards Installation If you need to install one or more A395x series mezzanine board on your DT5495 please contact CAEN to receive detailed instructions see Sect Technical Suppor...

Page 22: ...hown in Fig 7 2 CH0 CH0 CH1 CH1 CH16 CH16 CH17 CH17 CH14 CH14 CH15 CH15 CH30 CH30 CH31 CH31 N C N C N C N C Fig 7 2 Multi pin connector pin assignment The CAEN A967 Cable Adapter Fig 7 3 allows to ada...

Page 23: ...on with the board and allows the MFPGA Application firmware upgrade 2 OFF one or more FPGAs may not have been configured In case of a MFPGA configuration issue an attempt to force the MFPGA in Factory...

Page 24: ...Direct USB Driver Installation WINDOWS OS The Windows driver is available at the DT5495 webpage in the Software Firmware tab login required Note The following procedure is based on a Windows 10 syste...

Page 25: ...nual rev 0 25 4 Right click on V2495 item and select Update Driver Software option in the slide menu Fig 8 2 USB driver manual installation Step1 5 Select Browse my computer for driver software as in...

Page 26: ...rev 0 26 6 Use the Browse button to point to the driver folder in the destination path on the host PC Fig 8 4 USB driver manual installation Step3 7 Click the Close button at the end of the installat...

Page 27: ...rted by Linux kernels from kernel version 3 13 on This means that such kernel versions should be able to recognize the hardware automatically without requiring the user to install any driver Note the...

Page 28: ...e the Ethernet network of your PC in the following steps a Open the path Control Panel Network and Internet Network and Sharing Center Fig 8 13 Fig 8 7 The Network and Sharing Center window b Click on...

Page 29: ...ig 8 10 Properties window of the Internet Protocol Version TPC IPv4 Note Considering the factory default IP address of Hexagon is 192 168 0 90 use for the Network settings of the PC the same first thr...

Page 30: ...nterface will enter the Instrument Information page Fig 8 11 Fig 8 11 Instrument Information page of the DT5495 Web Interface Information includes the name the serial number the PCB revision the revis...

Page 31: ...of support requests CAENUpgrader can operate with Windows and Linux 32 and 64 bit OSs The software installation package can be downloaded from CAEN web site login required at the CAENUpgrader web pag...

Page 32: ...in the Board Model combo box 3 Set the connection parameters according to your communication link and hardware setup all the parameters are detailed in RD1 4 Select the MFPGA by checking the relevant...

Page 33: ...ade Firmware option in the Board tab 2 Select the V2495 item in the Board Model combo box 3 Set the connection parameters according to your communication link and hardware setup all the parameters are...

Page 34: ...8 and V1718 if supported The library includes a simple demo application which is not intended for the board readout but rather to automatically test the library functions The user can then inspect the...

Page 35: ...eadout throughput available This space can be accessed by using the available block transfer mechanism over the Ethernet or USB communication interfaces Block data transfer allows to implement a faste...

Page 36: ...oui1 0x8128 0x40 oui0 0x812C 0xE6 version 0x8130 0x00 board2 0x8134 0x00 board1 0x8138 0x09 board0 0x813C 0xBF revis3 0x8140 0x00 revis2 0x8144 0x00 revis1 0x8148 0x00 revis0 0x814C PCB revision sern...

Page 37: ...s signal Others reserved for future options Scratch Register Bit Description 31 0 This register allows to perform 32 bit accesses for test purposes Default value is 0xAAAAAAAA Flash Configuration 0x85...

Page 38: ...e of these demos together with a template firmware can be downloaded from the CAEN website When developing custom projects it is recommended to start with the included template firmware as it includes...

Page 39: ...tput The signals used are the following SIGNAL NAME WIDTH TYPE DESCRIPTION GIN 2 Input Input values for G0 G1 GOUT 2 Output Output values for G0 G1 SELG Output NIM TTL selector 0 NIM 1 TTL nOEG Output...

Page 40: ...n with signal X 16 and its status can be read from X 18 User LEDs Refer to the eight User LEDs on the front panel see Chap 4 SIGNAL NAME WIDTH TYPE DESCRIPTION LED 8 Output LED drivers Tab 10 6 LED po...

Page 41: ...10 8 SIGNAL NAME WIDTH TYPE DESCRIPTION nLBRES 1 Input Bus reset active low nBLAST 1 Input Last cycle active low WnR 1 Input Write Read cycle 0 read 1 write nADS 1 Input Address strobe active low nREA...

Page 42: ...or r w data transfer It can also be used for the data prefetch mechanism see next nBLAST OUT AL it signals the last cycle of a data transfer It is set when either the LBS is not ready or the LBM canno...

Page 43: ...request is pending and the local bus master has available space into the prefetch queue it will start an internal block transfer from local bus address 0x0000 fixed The User logic is required to respo...

Page 44: ...Nd 0 Ttrail 0 if Nd Ng 0 T0 T1 Nd Ng 1 if Nd Ng 1 The relationship between Tlead Ttrail and the delay and gate duration is Tdelay Tlead Tgate Ttrail Tlead Fig 10 5 Gate and Delay parameters represent...

Page 45: ...written here before it is transmitted through SPI to the GDG Address 0x7F00 Mode Read only Bit Description 31 0 Gate or delay datum to transmit to the GDG COMMAND register it is where the action to be...

Page 46: ...isters quoted are accessible via VME Set a delay gate value in the DATA WRITE register Set the COMMAND register to 0x2000 0x3000 to modify the delay gate internal value Set the control register to 0x1...

Page 47: ...re mapped at 16 bit aligned addresses while DT5495 features a 32 bit aligned address map Register access should always be in 32 bit mode o Common registers with different address 0x800C in V1495 0x820...

Page 48: ...0 ON others OFF Demo4 LED 2 ON others OFF 11 2 Demo Structure All demo projects feature a common file structure A configuration file V2495_package vhd allowing to set the number of CONFIG and MONITOR...

Page 49: ...x1010 0x1800 0x1804 0x1808 0x180C Firmware version Value of port A input Value of port B input Value of port C output Status register Mask of input port A Mask of input port B Control register User Va...

Page 50: ...8 Allows to select the signal type on ports G0 G1 0 NIM level 1 TTL level 7 6 Reserved 5 The gate of input port C ends when this bit is set 4 The gate of input port C starts when this bit is set 3 0...

Page 51: ...ation UM6508 DT5495 User Manual rev 0 51 C PORT USER VALUE register Allows to set the C port value when Control register bits 3 0 are set to 0x9 0xF Address 0x180C Mode Read and Write Bit Description...

Page 52: ...of the supported levels NIM or TTL should be provided All registers are 32 bit wide and can be accessed in single access mode ADDRESS REGISTER CONTENT ACCESS MODE Read Write 0x0000 0x1000 0x1004 0x10...

Page 53: ...o 1 means that the corresponding channel of port B is masked CONTROL register allows to set the demo configuration Address 0x1808 Mode Read and Write Bit Description 31 20 Number of stored samples in...

Page 54: ...R W Register Description FIRMWARE VERSION register Stores the revision number of the firmware Address 0x1000 Mode Read only Bit Description 31 0 Revision Number MEZZANINE ID NUMBER register Contains...

Page 55: ...ns the DAC value of the channel specified by bits 21 16 of the register 0x1800 Address 0x1804 Mode Read and Write Bit Description 31 0 DAC value Please note that the DAC value obtained from register 0...

Page 56: ...SS MODE Read Write 0x1000 0x1800 0x1804 Firmware Version Control register Clock frequency register A24 A32 A24 A32 A24 A32 D16 D32 D16 D32 D16 D32 R R W R W The registers of the Gate and Delay control...

Page 57: ...te internal buffer 0x3 The content of the Data write register is written in the delay internal buffer Control register 1 1 0x2 The gate value of the channel specified by 7 0 is read 0x3 The delay valu...

Page 58: ...rev 0 58 STATUS register Address 0x7F10 Mode Read only Bit Description 31 1 reserved 0 Gate and delay ready signal when 0 the Gate and Delay controller is busy A new command to the Gate and Delay cont...

Page 59: ...ual rev 0 59 12 Software Development Software applications can be developed for the DT5495 by using the functions and features provided by the CAEN PLULib library RD3 CAEN PLULib library requires the...

Page 60: ...d submitted from the Returns and Repairs area at Home Support Services with a detailed description of the specific failure A printed copy of the PRF must also be included in the package to be shipped...

Page 61: ...including engineers scientists and technical professionals who all trust them to help achieve their goals faster and more effectively CAEN S p A CAEN GmbH CAEN Technologies Inc Via Vetraia 11 Klingen...

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