PMCDIO64
Copyright
2000 BVM Ltd.
4
3. Operation
3.1 Block
Diagram
PLX PCI9030
PCI to Local Bus
Interface
PCI Bus
16 bit local bus
Xilinx SpartanXL
for
Logic Functions
Config.
EEPROM
Config.
EEPROM
Watchdog
Xtal
32.768kHz
5V
tolerant
3.3V
Buffer
External
Connection
Figure 3 Block Diagram
3.2
PCI9030 PCI Interface
The PMCDIO64 uses a PLX PCI9030 PCI interface to a 16-bit local bus on-board. The general
features of the PCI9030 are listed below.
•
PCI Local Bus Specification V2.2-compliant 32-bit, 33 MHz Bus Target Interface Device
enabling PCI Burst Transfers up to 132 MB/s.
•
PCI Bus Power Management Interface Specification V1.1 compliant.
•
PCI Local Bus Specification V2.2 Vital Product Data (VPD) configuration support.
•
PCI Target Programmable Burst Management.
•
PCI Target Read Ahead mode.
•
PCI Target Delayed Read mode.
•
PCI Target Delayed Write mode.
•
Programmable Interrupt Generator/Controller.
•
Two programmable FIFOS for zero wait state burst operation.
•
Flexible Local Bus provides 32-bit Multiplexed or Non-Multiplexed Protocol for 8, 16, or 32-bit
Peripheral and Memory devices.
•
Serial EEPROM interface.
•
Nine programmable General Purpose I/O (GPIOS).
•
Five programmable Local Address spaces.
•
Four programmable independent chip selects.
•
Programmable Local Bus wait states.
•
Programmable Local Read pre-fetch mechanism.
•
Local Bus can run asynchronously to the PCI Bus.
•
Two programmable Local-to-PCI interrupts.
•
Endian Byte Swapping.
Note that not all of these features are pertinent to the PMCDIO64 - see section "A.1 PCI9030 PCI
Interface (on page 17)" for further details of the device.
