BVM PMCDIO64, User Manual

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7.3.6.1 Watchdog Interrupt Enable (Bit 3: WINEN) ........................................................ 14
7.3.6.2 Global Output Enable (Bit 4: GOPEN) ................................................................ 14
7.3.6.3 Internal Watchdog Enable (Bit 6: IWDEN).......................................................... 14
7.3.6.4 Watchdog Status (Bit 7: WDGST) ...................................................................... 14
7.3.6.5 Input Lock (Bit 12: INLOCK) ............................................................................... 14
7.3.6.6 Output Hold (Bit 13: OUTHLD) ........................................................................... 14
7.3.6.7 Interrupt On Change-of-State Enable (Bit 14: IOCEN) ....................................... 14
7.3.6.8 Interrupt On Change-of-State Status (Bit 15: IOCST)......................................... 14
7.3.7 Watchdog Trigger Register .................................................................................................. 15
7.3.8 Watchdog Timer Register .................................................................................................... 15
7.3.9 Watchdog Status Register.................................................................................................... 15
7.4 Interrupts ..................................................................................................................................15
7.5 Windows
®
Driver Disc ..............................................................................................................15
8. Specification ...................................................................................................................................16
8.1 On-Board Functions .................................................................................................................16
8.1.1 PCI9030 PCI Interface.......................................................................................................... 16
8.1.2 SpartanXL FPGA .................................................................................................................. 16
8.1.3 Local Clocks.......................................................................................................................... 16
8.2 Board Configuration .................................................................................................................16
8.3 I/O Interface .............................................................................................................................16
8.4 PMC Interface ..........................................................................................................................16
8.5 Operating Environment ............................................................................................................16
Appendix A - Data Sheets & Manual References ...............................................................................17
A.1 PCI9030 PCI Interface .............................................................................................................17
A.2 Spartan-XL FPGA ....................................................................................................................17
A.3 74ABT16245A Buffers .............................................................................................................17
A.4 PMC Specification ....................................................................................................................17
List of Figures
Figure Page
Figure 1 Board Layout Topside ............................................................................................................... 2
Figure 2 Board Layout Underside ........................................................................................................... 2
Figure 3 Block Diagram........................................................................................................................... 4
Figure 4 Link Positions ............................................................................................................................ 8
Figure 5 Connector Pin-outs for 9-pin D-type........................................................................................ 11