BVM PMCDIO64 User Manual Download Page 14

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PMCDIO64



2000 BVM Ltd.

5. Configuration

5.1 Link

Positions

Figure 4 Link Positions

5.2 Link

Definitions

The following link definitions refer to the link positions as the shown above, i.e. with the PMC Front
Panel connector to the right. Pin 1 is denoted by a filled in pin position. Link positions marked with a

below show the default configuration.

5.2.1

LK1 to LK8 I/O Pull-Up Enable

The digital I/O signals to the PMCDIO64 may be pulled-up to +5V via 10K

Ω

resistor networks in

groups of 8 if link selected. See the table below for link to I/O equivalence.

OPERATION

LINK

FITTED

OMITTED

LK1

Pull-up IO0 - IO7 via 10K

Ω

IO0 - IO7 NOT pulled-up

LK2

Pull-up IO8 - IO15 via 10K

Ω

IO8 - IO15 NOT pulled-up

LK3

Pull-up IO16 - IO23 via 10K

Ω

IO16 - IO23 NOT pulled-up

LK4

Pull-up IO24 - IO31 via 10K

Ω

IO24 - IO31 NOT pulled-up

LK5

Pull-up IO32 - IO39 via 10K

Ω

IO32 - IO39 NOT pulled-up

LK6

Pull-up IO40 - IO47 via 10K

Ω

IO40 - IO47 NOT pulled-up

LK7

Pull-up IO48 - IO55 via 10K

Ω

IO48 - IO55 NOT pulled-up

LK8

Pull-up IO56 - IO63 via 10K

Ω

IO56 - IO63 NOT pulled-up

Summary of Contents for PMCDIO64

Page 1: ... I O PMC Module Board Revision A Manual Revision B 04 April 2001 This material contains information of proprietary interest to BVM Ltd It has been supplied in confidence and the recipient by accepting this material agrees that the subject matter will not be copied or reproduced in whole or in part nor its contents revealed in any manner or to any person except to meet the purposes for which it was...

Page 2: ...This page is intentionally left blank ...

Page 3: ...s provided as Copyright BVM Ltd is proprietary and confidential property of BVM Ltd and each single copy is given on the agreed understanding that it is licensed for use on product combinations supplied by BVM Ltd or their appointed distributors only The software product may not be copied except for backup purposes given away rented loaned reproduced distributed or transmitted in any way or form i...

Page 4: ...ii This page is intentionally left blank ...

Page 5: ...r 5 3 3 8 Watchdog Timer Register 5 3 3 9 Watchdog Status Register 5 3 4 I O Interface 6 3 5 93CS56 EEPROM 6 3 6 18V256 EEPROM 6 4 Installation 7 5 Configuration 8 5 1 Link Positions 8 5 2 Link Definitions 8 5 2 1 LK1 to LK8 I O Pull Up Enable 8 5 2 2 LK9 to LK12 P5 Common Select 9 6 Connections 10 6 1 Front Panel Connector 10 6 2 Rear I O Connector 11 6 3 PMC I O Board 11 6 4 PCI Connections 12 7...

Page 6: ...15 7 3 9 Watchdog Status Register 15 7 4 Interrupts 15 7 5 Windows Driver Disc 15 8 Specification 16 8 1 On Board Functions 16 8 1 1 PCI9030 PCI Interface 16 8 1 2 SpartanXL FPGA 16 8 1 3 Local Clocks 16 8 2 Board Configuration 16 8 3 I O Interface 16 8 4 PMC Interface 16 8 5 Operating Environment 16 Appendix A Data Sheets Manual References 17 A 1 PCI9030 PCI Interface 17 A 2 Spartan XL FPGA 17 A ...

Page 7: ...l software engineers and end users This User s Manual covers details of the PMCDIO64 only which is one in a range of PMCDIO digital I O and PMCCTR counter timer I O PMC modules from BVM Unless otherwise stated address information is in hexadecimal notation 1 2 PMCDIO64 Part Numbers Part Number Type Description 853 11111 PMCDIO64 64 bit TTL digital I O change of state A Windows driver disc is avail...

Page 9: ...double sampled on 33Mhz PCI clock Watchdog period programmable 125ms to 2sec Watchdog interrupt Watchdog tri states outputs Front panel and rear I O connections Conforms to PMC standard IEEE P1386 1 Draft 2 3 9 th October 2000 Conforms to PCI Local Bus Specification Revision 2 2 2 3 Applications Interfacing industrial equipment General purpose industrial I O 32 bit or 64 bit data I O Fail safe con...

Page 10: ...duct Data VPD configuration support PCI Target Programmable Burst Management PCI Target Read Ahead mode PCI Target Delayed Read mode PCI Target Delayed Write mode Programmable Interrupt Generator Controller Two programmable FIFOS for zero wait state burst operation Flexible Local Bus provides 32 bit Multiplexed or Non Multiplexed Protocol for 8 16 or 32 bit Peripheral and Memory devices Serial EEP...

Page 11: ...s set to 1 output is enabled otherwise input is enabled 3 3 5 Function Register An 8 bit Function Register which contains the low byte of the PCI Subsystem Device ID used to determine the type of board fitted from the PMCDIO and PMCCTR range 3 3 6 Control Status Register A 16 bit Control Status Register where the bits are used to control and monitor the status of the following functions Watchdog I...

Page 12: ...Select on page 9 for further details 3 5 93CS56 EEPROM The PMCDIO64 is fitted with a 93CS56 EEPROM which is supplied pre programmed by BVM The contents of this EEPROM are read by the PCI9030 on coming out of reset and are used to set up the control registers after reset configuring the PCI interface configuration PCI Device Vendor ID s various other board specific parameters See section 7 1 PCI Co...

Page 13: ...he PMC module front panel 3 The PMC module should be fixed to the host carrier using four M2 5 x 6mm pan head screws into the four fixing holes provided two on the front panel and two on the spacers 4 There is no voltage keying on the PMCDIO64 it will work in both 3 3V and 5V host carriers 5 The PMCDIO64 can be used with a BVM supplied connecting lead to standard 9 pin D type connectors or a user ...

Page 14: ...als to the PMCDIO64 may be pulled up to 5V via 10KΩ resistor networks in groups of 8 if link selected See the table below for link to I O equivalence OPERATION LINK FITTED OMITTED LK1 Pull up IO0 IO7 via 10KΩ IO0 IO7 NOT pulled up LK2 Pull up IO8 IO15 via 10KΩ IO8 IO15 NOT pulled up LK3 Pull up IO16 IO23 via 10KΩ IO16 IO23 NOT pulled up LK4 Pull up IO24 IO31 via 10KΩ IO24 IO31 NOT pulled up LK5 Pu...

Page 15: ...ch allow 4 pins to be used as commons for the other 64 I O signal connections The commons may be individually selected as 5V fused GND or not connected OPERATION LINK FITTED 1 TO 2 FITTED 2 TO 3 OMITTED LK9 COM0 5V COM0 GND COM0 N C LK10 COM1 5V COM1 GND COM1 N C LK11 COM2 5V COM2 GND COM2 N C LK12 COM3 5V COM3 GND COM3 N C ...

Page 16: ...0 7 IO6 P1 4 P5 4 IO38 41 8 IO7 P1 9 P5 9 IO39 42 9 IO8 P2 1 P6 1 IO40 43 10 IO9 P2 6 P6 6 IO41 44 11 IO10 P2 2 P6 2 IO42 45 12 IO11 P2 7 P6 7 IO43 46 13 IO12 P2 3 P6 3 IO44 47 14 IO13 P2 8 P6 8 IO45 48 15 IO14 P2 4 P6 4 IO46 49 16 IO15 P2 9 P6 9 IO47 50 17 COM0 P1 5 P2 5 P5 5 P6 5 COM2 51 18 COM1 P3 5 P4 5 P7 5 P8 5 COM3 52 19 IO16 P3 1 P7 1 IO48 53 20 IO17 P3 6 P7 6 IO49 54 21 IO18 P3 2 P7 2 IO5...

Page 17: ... IO11 IO43 24 25 IO12 IO44 26 27 IO13 IO45 28 29 IO14 IO46 30 31 IO15 IO47 32 33 IO16 IO48 34 35 IO17 IO49 36 37 IO18 IO50 38 39 IO19 IO51 40 41 IO20 IO52 42 43 IO21 IO53 44 45 IO22 IO54 46 47 IO23 IO55 48 49 IO24 IO56 50 51 IO25 IO57 52 53 IO26 IO58 54 55 IO27 IO59 56 57 IO28 IO60 58 59 IO29 IO61 60 61 IO30 IO62 62 63 IO31 IO63 64 6 3 PMC I O Board If required a SCSI III style lead can be used to...

Page 18: ... AD 29 20 21 AD 28 AD 27 22 21 Ground AD 26 22 23 AD 25 Ground 24 23 AD 24 3 3V 24 25 Ground C BE 3 26 25 IDSEL AD 23 26 27 AD 22 AD 21 28 27 3 3V AD 20 28 29 AD 19 5V 30 29 AD 18 Ground 30 31 V I O AD 17 32 31 AD 16 C BE 2 32 33 FRAME Ground 34 33 Ground PMC RSVD 34 35 Ground IRDY 36 35 TRDY 3 3V 36 37 DEVSEL 5V 38 37 Ground STOP 38 39 Ground LOCK 40 39 PERR Ground 40 41 SDONE SBO 42 41 3 3V SERR...

Page 19: ...the output signals no account is taken of values beyond the I O buffers To read a 64 bit register requires two 32 bit PCI read cycles each of which generates two 16 bit read cycles on the local bus As data consistency across the register cannot be guaranteed an input lock bit is provided in the Status Control Register see section 7 3 6 5 Input Lock Bit 12 INLOCK on page 14 when this bit is set the...

Page 20: ...ected as outputs are disabled Input signals are unaffected 7 3 6 3 Internal Watchdog Enable Bit 6 IWDEN When set to 1 the internal watchdog function is enabled and if the watchdog times out then the outputs will be disabled If clear the state of the watchdog is ignored 7 3 6 4 Watchdog Status Bit 7 WDGST When set to 1 this bit indicates an enabled internal watchdog has timed out see section 7 3 6 ...

Page 21: ...riod 0 125ms 1 250ms 2 500ms 3 1 0sec 4 2 0sec 5 2 0sec 6 2 0sec 7 2 0sec 7 3 9 Watchdog Status Register The 8 bit read only Watchdog Status Register is used to determine the status of the watchdog When bit 0 is read as 1 the watchdog function is enabled when bit 1 is read as 1 the watchdog function has been started bits 7 2 are undefined when read Note that writing to this register whilst the int...

Page 22: ...r Register Watchdog Timer Register Watchdog Status Register 8 1 3 Local Clocks 32 768KHz timer clock 8 2 Board Configuration LINKS Pull Up enables Common Selection EEPROM PCI Configuration FPGA Configuration 8 3 I O Interface 64 bits of TTL compatible I O I O direction byte selectable Global output enable 74ABT16245A buffers 32mA source capability 64mA sink capability Re settable fuse protected at...

Page 23: ...GA Spartan and SpartanXL Families Field Programmable Gate Arrays DS060 V1 5 March 2 2000 http www xilinx com A 3 74ABT16245A Buffers SN54ABT16245A SN74ABT16245A 16 bit Bus Transceivers with 3 State Outputs SCBS300E March 1994 Revised March 1999 http www ti com A 4 PMC Specification IEEE Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC P1386 1 Draft 2 3 9 th October 2000...

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