PMCDIO64
Copyright
2000 BVM Ltd.
5
3.3 Main
Logic
The PMCDIO64 uses a Xilinx SpartanXL FPGA connected to the 16-bit local bus to provide the on-
board logic functions as described below.
3.3.1 Input
Register
A 64-bit Input Register containing a latched version of the I/O pins on the logic device. The signal is
latched by the 33MHz PCI clock.
3.3.2 Output
Register
A 64-bit Output Register whose contents are output to valid output pins.
3.3.3
Change Flags Register
A 64-bit Change Flags Register where each bit indicates an input that has changed state since
interrupt on change-of-state was enabled.
3.3.4 Direction
Register
An 8-bit Direction Register where each bit corresponds to a group of 8 I/O bits. If the corresponding bit
is set to 1 output is enabled otherwise input is enabled.
3.3.5 Function
Register
An 8-bit Function Register which contains the low byte of the PCI Subsystem Device ID - used to
determine the type of board fitted from the PMCDIO and PMCCTR range.
3.3.6
Control & Status Register
A 16-bit Control & Status Register where the bits are used to control and monitor the status of the
following functions.
•
Watchdog Interrupt Control.
•
Global Output Control.
•
Watchdog Enable Control.
•
Watchdog
Status.
•
Lock Inputs Control.
•
Hold Outputs Control.
•
Change-of-State Interrupt Control.
•
Change-of-State
Status.
3.3.7
Watchdog Trigger Register
A 8-bit register in which bit 0 must be written alternately 0 and 1 within
±
25% of the watchdog refresh
period.
3.3.8
Watchdog Timer Register
An 8-bit register defining the watchdog refresh period: 125ms; 250ms; 500ms; 1sec or 2sec.
3.3.9
Watchdog Status Register
An 8-bit register which indicates if the watchdog has timed out.
