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CHAPTER 3 THEORY OF OPERATION
Confidential
3-6
1.3.3 IEEE1284
interface
Stores the data received from the PC into DRAM by DMA using the Gate Array
(UPD65421MC-11) exclusive for parallel I/F. It is for the normal receipt and dual direction
communication (nibble mode, byte mode, ECP mode).
< HL-2040 >
5
DI4
@C114
C101
0V
TP146
0V
VDD5
1-5F
CDCC_RSTN
@RA3
100
2
7
1
8
3
6
4
5
17
0V
26
0V
32
FLT
VDD5
TP157
7
DI6
IF_FG2
31
INPRIM
1
STB
VDD5
@C98
C101
@R131
100
TP156
@R124
1.5k
@RA5
1.5k
2
7
1
8
3
6
4
5
@C117
C101
TP150
@C97
C103
37
FG
9
DI8
1-5F
CDCC_DATA
22
0V
@C100
C103
@R121
0
35
NC
@C108
C101
30
0V
28
0V
@CN10
10
ACK
@C120
C101
@RA7
100
2
7
1
8
3
6
4
5
@ZD5
UDZS6.8B
TP155
15
NC
11
BUSY
0V
@DA4
DF5A6.8FU
C3
C1
C2
A
C4
34
NC
@C106
C101
TP148
23
0V
@C112
C104
VDD3
24
0V
1-5F
CDCC_CLK
@C128
C101
@RA4
0
2
7
1
8
3
6
4
5
13
SELECT
@C115
C101
6
DI5
VDD5
0V
18
+5V
@RA2
1.5k
2
7
1
8
3
6
4
5
@C125
C101
@C127
C101
@R5
100
@C109
C101
@RA6
2.2k
2
7
1
8
3
6
4
5
@DA2
DF5A6.8FU
C3
C1
C2
A
C4
25
0V
@C129
C101
27
0V
TP158
57RE40360-730B-D29
38
FG
20
0V
@R132
100
19
0V
@C111
C101
@DA3
DF5A6.8FU
C3
C1
C2
A
C4
16
0V
@RA8
100
2
7
1
8
3
6
4
5
@R2
100
@C110
C101
0V
12
PE
0V
@RA9
2.2k
2
7
1
8
3
6
4
5
1-5F
CDCC_INTN
@C118
C101
@DA1
DF5A6.8FU
C3
C1
C2
A
C4
21
0V
2
DI1
1-5F
CDCC_REQN
TP154
3
DI2
4
DI3
36
SELIN
@C113
C101
29
0V
14
ATFEED
IF_FG3
@C121
C101
TP161
0V
33
NC
8
DI7
@R134
1k
TP159
@U12
CDCC-GA
RSTN/SIN
21
INTN
24
REQN/SOUT
22
CLK/SCK
25
DATA
23
AMC
13
SMC
20
VDD51
1
VDD57
7
VDD516
16
GND26
26
VDD3
30
GND15
15
ACKN
6
BUSY
5
PE
4
SELECT
3
FLTN
28
AFN
2
SELINN
29
INITN
27
STBN
17
D0
18
D1
19
D2
14
D3
12
D4
11
D5
10
D6
9
D7
8
@L11
BLM18PG181SN1
@L12
BLM18PG181SN1
@C143
C104
(1608)
VDD5
TP190
TP191
NC
NC
NC
NC
CDCC_0V
CDCC_0V
CDCC
CDCC_GA
Fig. 3-7