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HL-2030/2040/2070N SERVICE MANUAL
Confidential
3-3
1.3 Main
PCB
For the entire circuit diagram of the main PCB, see
APPENDIX 1. to 6. ‘MAIN PCB CIRCUIT
DIAGRAM’
in this manual.
1.3.1 CPU
A Fujitsu 32bit RISC CPU, SPARClite is built in the ASIC. While the CPU is driven with a clock
frequency of 48.00 MHz (HL-2030/2040) or 66.66 MHz (HL-2070N) in the user logic block, it
itself runs at 96.0 (HL-2030/2040) or 133.0 MHz (HL-2070N), which is generated by multiplying
the source clock by two.
< HL-2030/2040 >
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
ADR[7]
ADR[8]
ADR[9]
ADR[10]
ADR[11]
ADR[12]
ADR[13]
ADR[14]
ADR[15]
ADR[16]
ADR[17]
ADR[18]
ADR[19]
ADR[20]
ADR[21]
ADR[4]
ADR[5]
ADR[6]
ADR[1]
ADR[2]
ADR[3]
ANALOG
ANALOG
ANALOG
ANALOG
ANALOG
ANALOG
ADR[22]
TP141
0V
VDD3
R115
33k
VDD3
R114
180
5C/6A/6B
ADR[22-1]
6A
SDCSN0
6B
SDCLK0
7A
ROMCSN0
7A
IORDN
0V
@C11
0
@C16
C10P
@R19
3.3k
@R20
100
@X1
AT-49 33.333333MHZ
1
2
TP17
0V
C76
C5P
R85
2.2k
R86
330
TP116
X2
AT-49 48.00MHZ
1
2
C75
C5P
2-4D
SCAN_CTL
2-6C
SCANNER_FGS
2-7D
MAIN_CTL
2-7D
MAIN_F/R
2-7E
MAIN_FGS2
5E
USBVCC
5E
USBCTL
5E
USBDP
5E
USBDN
7A
IOWEN
2D
DBRXD
2D
DBTXD
2-6B
FAN12V
2-6A
FAN24V
5C
DATA[15-0]
8E
EESDA
7E
EESCL
PI1
SG-206S
A
K
E
C
5D
VBDN
2-1A
HEATERON
2-1A
RLYOFFN
2-1A
HTLIMITN
2-2F
PNLLED0
2-2F
PNLLED1
2-2F
PNLLED2
2-2F
PNLLED3
2-2E
SOL1
2-2E
SOL2
2-2D
HVPWMDEV
2-2D
HVPWMTRCV
2-2D
HVPWMTRCC
2-2D
HVPWMCHG
2-2B
REG_FRONT_SEN
2-2D
REG_REAR_SEN
2-2F
FRONT_COVER_SEN
2-2F
PNEW_SEN
2-2B
PEDG_SEN
2-2F
PNLSW0
2-2B
THM1
2-2C
FB_TR
2-2C
FB_TRCCV
2-2C
FB_GRID
2-2C
FB_DEV
2-2C
FB_VCLN
R29
10k
R109
10k
R104
10k
R102
10k
R100
10k
R93
10k
VDD3
R33
10k
R110
10k
R108
10k
0V
R36
10k
VDD3
R73
10k
@R31
10k
R7
10k
R6
10k
@R4
10k
R3
10k
TP113
TP121
TP127
TP135
TP133
TP124
TP97
0V
TP117
TP109
TP95
TP53
TP44
TP79
TP46
TP70
TP87
TP115
TP92
TP83
TP131
TP75
TP102
TP76
TP63
TP62
TP61
TP67
TP60
TP66
TP59
TP81
TP94
TP120
TP123
TP96
TP103
TP111
TP108
TP112
TP100
TP106
TP105
TP91
TP99
TP4
TP5
TP32
TP89
TP31
TP14
TP7
TP1
TP2
TP6
2-2C
GRIDC
VDD3
R1
10k
0V
VDD3
2-5B/2-7B
SENSE
2-8C
MAIN_FGS
U4
Bellona
DATA00
138
DATA01
139
DATA02
140
DATA03
141
DATA04
142
DATA05
143
DATA06
2
DATA07
3
DATA08
4
DATA09
5
DATA10
6
DATA11
8
DATA12
9
DATA13
10
DATA14
11
DATA15
12
UCKOUT
31
UCKIN
29
SCKIN
27
VCKOUT
85
VCKIN
87
USBVCC
102
DBRXD
82
VBDN
80
HTLIMITN
25
SCANFGS
73
DCFGS
35
PNLSW0
59
SEN0
52
SEN1
51
SEN2
50
SEN3
49
SEN4
20
TNRLED
53
HVNOISE
69
AI0
39
AI1
40
AI2
41
AI3
42
AI4
43
AI5
44
AI6
45
AI7
46
ADR1
111
ADR2
112
ADR3
113
ADR4
116
ADR5
117
ADR6
118
ADR7
119
ADR8
120
ADR9
121
ADR10
122
ADR11
123
ADR12
124
ADR13
125
ADR14/BA0
126
ADR15/BA1
130
ADR16/RASN
131
ADR17/CASN
132
ADR18/WEN
133
ADR19/DQM0
134
ADR20/DQM1
135
ADR21
136
ADR22
137
ROMCSN0
15
IOWEN
16
IORDN
17
SDCLK0
18
SDCSN0
19
EESCL
95
EESDA
94
USBCTL
101
USBDP
98
UDBDN
99
DBTXD
83
VSH
81
HEATERON
23
RLYOFFN
24
FAN24V
21
FAN12V
22
SCANCTL
74
DCCTL
34
DCFR
33
PNLLED0
60
PNLLED1
61
PNLLED2
62
PNLLED3
63
SOL1
48
SOL2
47
HVVCLN
67
HVPWMVCLN
70
HVPWMDEV
68
HVPWMTRCV
64
HVPWMTRCC
65
HVPWMCHG
66
REV1
72
PORT00
71
PORT01
36
PORT02
26
PORT03
75
PORT04
104
PORT05
105
PORT06
106
PORT07
107
PORT08
108
2-7C
MAIN_START
2-2D
TNR_SEN
2-3B
TNRLED
R34
10k
VDD3
R28
1k
VDD3
0V
VDD3
VDD3
3-1B
CDCC_RSTN
3-1C
CDCC_DATA
3-1C
CDCC_CLK
3-1C
CDCC_REQN
3-1B
CDCC_INTN
0V
2-2D
HVPWMVCLN
TP42
@R30
10k
0V
L9
0
L10
0
TP181
TP182
TP189
Ic=3.3V/33k
=97
A
EJECT SENSOR
33.3333MHz
XTAL
48.00MHz
XTAL
(5Vtol)
(5Vtol)
(5Vtol)
(5Vtol)
(5Vtol)
(5Vtol)
(5Vtol)
(5Vtol)
(5Vtol)
If=(3.3V-1.2V)/180
=11.7mA
P=(11.7mA)^2*180
=1/41W
Fig. 3-3