BBK PV420S, Service Manual

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210
© 1999 Silicon Storage Technology, Inc. 336-04 1/99
2 Megabit Multi-Purpose Flash
SST39VF020
Preliminary Specifications
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
T
ABLE
3: O
PERATION
M
ODES
S
ELECTION
Mode CE# OE# WE# A9 DQ Address
Read V
IL
V
IL
V
IH
A
IN
D
OUT
A
IN
Program V
IL
V
IH
V
IL
A
IN
D
IN
A
IN
Erase V
IL
V
IH
V
IL
X X Sector address, XXh for
chip erase
Standby V
IH
X X X High Z X
Write Inhibit X V
IL
X X High Z/D
OUT
X
X X V
IH
X High Z/D
OUT
X
Product Identification
Hardware Mode
V
IL
V
IL
V
IH
V
H
Manufacturer Code (BF) A
17
- A
1
= V
IL
, A
0
= V
IL
Device Code (D6) A
17
- A
1
= V
IL
, A
0
= V
IH
Software Mode V
IL
V
IL
V
IH
A
IN
ID Code See Table 4
336 PGM T3.0
T
ABLE
2: P
IN
D
ESCRIPTION
Symbol Pin Name Functions
A
17
-A
0
Address Inputs To provide memory addresses. During sector erase A
17
-A
12
address lines
will select the sector.
DQ
7
-DQ
0
Data Input/output To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the write operations.
V
DD
Power Supply To provide 2.7-3.6V supply
Vss Ground
NC No Connection Unconnected pins
336 PGM T2.1