Innovator CU10BT-CU5000BT Analog Transmitter
Board Descriptions
Instruction Manual, Rev. 0
46
Frequency Response Corrector Circuit
The output of Z2 at Port 2 connects to the first corrector stage of the three-stage
frequency-response corrector circuit. The three stages are adjusted as needed to attain
the best response across the bandwidth. The frequency-response corrector circuit
operates as follows. Variable resistors R24, R25 and R26 are used to adjust the depth
and gain of the notches and variable caps C14, C15 and C16 are used to adjust the
frequency position of the notches. These are adjusted as needed to compensate for
frequency response problems. The jumpers W1 on J4, W2 on J5 and W3 on J6 are
moveable to set the frequency response of the circuits for 44 MHz, which is between
pins 2 & 3 or between 1 & 2 for 36 MHz.
The Non-Linear and Frequency Response pre-corrected IF is connected to the op-amp
U2. After amplification, the IF is split with one path connected through a divider
network to J1 the IF output jack on the board, -12 dBm. The other path is fed through a
divider network to J3 the IF Sample Jack, –18dBm.
ALC Circuit
The other non-linear pre-corrector output of Z2 at Port 1 connects to the input of the ALC
circuit. The IF signal is applied to the transformer T1, which doubles the voltage swing by
means of a 1:4 impedance transformation. It is connected to the ALC detector circuit,
consisting of C11, CR4 and R21. The detected ALC level output is amplified by U3A and
wired to U3B, pin 6, where it is summed with the power control setting of R40 the ALC
Adjust pot.
The output of U3B connects through S1 pins 2 to 3, if it is in the ALC position, to the pin-
diode attenuator circuit, CR1, CR2 & CR3. The high forward biases them more or less,
that increases or decreases the IF level, therefore the output level. When the input signal
level increases, the forward bias on the pin attenuator decreases, therefore the output
power decreases, that maintains the output power as set by the customer.
The ALC voltage is set for 1.0 VDC at TP1 with a –12 dBm peak sync output as measured
at J1 of the board. The ALC action starts with the ALC detector level monitored at TP1.
The detector output at TP1 is nominally, 1.0 VDC, and is applied through resistor R33 to a
summing point at op-amp U3B pin 6. The current available from the ALC detector is
offset, or complemented, by current taken away from the summing junction. In normal
operation, U3B pin 6, is at 0 VDC when the loop is satisfied. If the recovered or peak-
detected IF signal level at the IF input to this board should drop, which normally indicates
that the output power has decreased, the null condition no longer occurs at U3B pin 6.
When the level drops, the output of U3B pin 7 goes more positive. If S1 is in the
Automatic position, it will cause the ALC pin-diode attenuators CR1, CR2, and CR3 to have
less attenuation and therefore increase the IF level that will compensate for the decrease
in the output power level.
If the ALC cannot increase the input level enough to satisfy the ALC loop, due to the lack
of range, an ALC fault will occur. The fault is generated because U3C pin 9, increases
above the trip point set by R47 and R50 until it conducts. This makes U3C pin 8, high and
causes Q3 to conduct, which lights the Red ALC Fault LED DS1.
Summary of Contents for Innovator CU10BT/CU0T-1
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