Avtech AVRQ-5-B, Instructions Manual

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DUT WIRING, ON MAIN PCB
1 2 3 4 5 6
A
B
C
D
6 5 4 3 2 1
D
C
B
A
T i tle
Re vis i on Da te
3-May-2017
Z:\mjcfiles\pcb\266\avrq-5.Ddb - 266A2 (mod2)\DUT-manual.sch
DUT AREA
1A
VC C2 -PS
C5 0
0 . 1 u F
L4
0 . 1 u H
L3
4 3 4 -0 1 -4 71 J
C4 9
2 2 u F,5 0 V
1 2
-P
U
L
S
E
3 4 5 6
H
V
P
R
O
B
E
7 8 9
1
0
1
1
1
2
1
3
1
4
1
5
H
V
P
R
O
B
E
1
6
1
7
1
8
1
9
+
P
U
L
S
E
2
0
G
N
D
2
1
2
2
2
3
2
4
G
N
D
2
5
2
6
2
7
2
8
O
U
T
2
9
3
0
3
1
3
2
O
U
T
3
3
3
4
3
5
V
C
C
2
3
6
3
7
3
8
3
9
V
C
C
2
4
0
DU T1
ZIF4 0 SO CK ET, W ITH UN US ED PINS FU LLY RE MO VE D
P2
TO H V BN C
P1
TO H V BN C SHIELD
1
2
J4
SA M1 0 3 7 -0 1 -ND
FOR US ER 'S LOGIC P ROBE
FR OM P ULS ER C IR CU ITS
HV -PULS E-
HV -PULS E+
FR OM P OW E R SU PP LY CIRC UITS
FOR US ER 'S H V PR OB E
GN D2 VC C2
LOGIC OU TPU T
GN D1 (COMMON -MOD E HV P ULS E)
VC C1 IS GE NE RA TED ON THE D AU GH TE RB OA RD .