Avnet Xilinx Virtex-II, User Manual

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3 of 25 Rev 1.0 06/08/2004
Released Literature # ADS-xxxx04
Figures
Figure 1 - Fly Wire Connection J2 ................................................................................................................................................................. 6
Figure 2 - JTAG Chain..................................................................................................................................................................................... 8
Figure 3 – JP1.................................................................................................................................................................................................... 9
Figure 4 - I/O Voltage Selection.................................................................................................................................................................... 9
Figure 5 - Virtex-II Development Board Block Diagram........................................................................................................................11
Figure 6 - Virtex-II Development Board....................................................................................................................................................11
Figure 7 - Barrel Power Connector "J4" .....................................................................................................................................................23
Tables
Table 1: Ordering Information....................................................................................................................................................................... 5
Table 2 - JTAG Headers (JTAG3 & JTAG4) Pin-Out .............................................................................................................................. 6
Table 3 - Virtex-II Power-up Configuration Modes................................................................................................................................... 7
Table 4 - JTAG Boundary-Scan Description Language (BSDL) files...................................................................................................... 8
Table 5 - RS232 Connector Pin-out ............................................................................................................................................................12
Table 6 – LED Pin Assignment @ the FPGA ..........................................................................................................................................13
Table 7 –Switch Pin Assignment @ the FPGA.........................................................................................................................................13
Table 8 – General I/O AvBus Connector P2 & P3 .................................................................................................................................15
Table 9 – Low Voltage Differential Signaling Pairs (P3)..........................................................................................................................16
Table 10 – Memory I/O AvBus Connector P4 & P5 ..............................................................................................................................18
Table 11 – Auxiliary AvBus Connector P6 & P7 ......................................................................................................................................20
Table 12 – PCI/PCI-X Connector Pin Assignment and Interface Signals...........................................................................................22
Table 13 – Virtex-II Power-up Configuration Modes..............................................................................................................................24
Table 14 – System ACE Test Designs.........................................................................................................................................................24