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Avnet Design Services
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Rev 1.0 06/08/2004
Released
Literature # ADS-xxxx04
3.8 Evaluation
Boards
Evaluation boards primary purpose is being used as a stand-alone integration/evaluation tool. However, the evaluation board
pin-out is common to that of the backplane in the event integration between the two platforms is desired. Evaluation boards
interface to the Virtex-II Development backplane via the AvBus interfaces connector. Power sources for the board can be
reconfigured via jumpers to allow the card to be powered as a stand-alone unit as well powered via the backplane when
installed.
3.9 Extender Card Board
Provisions for an extender card interface may be incorporated on the development modules or boards, which have the same
pin assignment as the backplane connectors. This allows breakout capability of all connector signals for evaluation.
3.10 Power
The Virtex-II Development board uses a 5V AC/DC adapter (supplied with the kit) with center positive barrel connector.
The 5V is used as the input to a TI PT5401 which provides 3.3VDC. Two National Semiconductor LP3966-ADJ parts
provide 2.5V and 1.5V. The barrel connector “J4” is shown below in Figure 7. It should be noted that there is
no protection
for reverse power supply polarity
so take necessary precautions to ensure that the center pin is 4.5V – 5.5V, and the ring is
ground!
φ
0.076 in (1.93 mm)
pin diameter
φ
0.25 in (6.3 mm)
housing diameter
+5 Volts
GND
Figure 7 - Barrel Power Connector "J4"
3.10.1
FPGA I/O Voltage (Vcco)
Vcco selectable voltages are available on the Virtex-II Development Board to support the FPGAs various voltage standards.
The Virtex-II Development Board provides various selectable I/O voltages for FPGA banks 0,1,4 & 5, independent of each
other, to support the various I/O standards. The I/O voltages available are +3.3V, +2.5V, +1.8V and +1.5V, these I/O
voltage levels are available on header connectors JP12, JP13 & JP2.
3.10.2
FPGA Reference Voltage (Vref)
The Virtex-II Development Board provides various reference voltages for FPGA bank 0 and 1, independent of each other.
The reference voltages available are +1.65V, +1.5V, +1.25V, +.9V and +.75V (half the I/O voltage 1.5V which is
jumper selected). These reference voltages are available on header connector JP14 & JP15.
3.11 Configuration
Modes
Upon power-up the FPGA will be enabled in a configuration mode defined by jumper header JP1. The default
configuration mode is “Master-Serial” mode, which will allow the FPGA to be programmed from the System ACE MPM.
