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Avnet Design Services
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Rev 1.0 06/08/2004
Released
Literature # ADS-xxxx04
4.1 On-board Flash Test
The “On-board Flash Test” checks the interface to the Intel StrataFlash
device. The design uses a Xilinx MicroBlaze
soft
processor system containing the External Memory Controller peripheral to access the Flash. The MicroBlaze was used
because it is much easier to code memory tests in C/C++ than in hardware language and because of the drop-in UART
peripheral for the user interface. Type “help” at the prompt to view a list of commands. Type “flash” at the prompt to
execute the Flash Test. The Flash Test performs a pseudo-random memory test on a 256KB region of memory in the lower
4MB of the Flash and another 256KB region in the upper 4MB. The Flash Test also performs an address pin check where
each address pin is individually asserted to check for open connections and shorts.
4.2 PCI/PCI-X
Test
The “PCI Test” implements a basic target PCI design using the Xilinx PCI LogiCORE
. The design uses the internal
memory resources of the FPGA (block RAM) as PCI data buffers for the BAR0 and BAR1 regions. The buffers are 32KB or
1024x32 bits (BAR0/1 offset 0x0 to 0x3FF). This enables the user to perform single writes/read to the base address registers.
There is also a register in the BAR2 space (offset 0x8) that provides the user with the ability to write to the on-board LEDs.
The Virtex-II Development board supports PCI-X mode but is set-up for normal PCI with the default resistor settings (see
the schematic). To use the PCI design, set the MPM address to the "PCI Test" bit file and place a jumper on JP7 (labeled
+5V PCI) to connect the 5V input from the PCI slot to the 5V rail. Then plug the board into a PCI slot (do not hot plug the
board, the PC must be powered off). Turn on the PC. At this time the user should be able to read the configuration space of
the board over the PCI bus and perform single transfers to BAR0 and BAR1. There is a software program in the “Utilities”
folder on the CD called the “ADS PCI Utility”, which allows the user to perform basic PCI transactions to the Virtex-II
Development board.
4.3 Switch/LED
Test
The "Switch/LED Test" file simply drives a scanning pattern on the bank of 8 LEDs when dipswitch S1 position 1 is
depressed in the "on" or closed position. Dipswitch positions 2 through 8 each control one LED in the bank of 8 LEDs.
4.4 Avbus Connector Test
The "Avbus Connector Test" tests the electrical connectivity of the Avbus connectors. This test requires a custom test board
to perform the test. The test won't run or it will fail without having the custom test board installed.
4.5 DDR SDRAM Test
The DDR tester has a calibration function, which must be run before testing the memory. Type "plot" to show a plot of read
clock phase versus write clock phase. The plot shows the current phase values with an @ symbol, passing regions with an
asterisk and failed regions with a period. Type "cal" at the prompt to start the calibration function. Do another plot to see the
new phase setting (should be in the middle of the passing region). To run memory tests, type "test <start address> <end
address> <test type or blank for all tests>". For example, "test 0 8000000 rand" will perform the pseudo-random memory
test on the entire 128MB SODIMM.
5.0 Example VHDL Project
An example project is included on the CD to demonstrate the Project Navigator tool in the Xilinx Integrated Software
Environment (ISE) development suite. The source code was written in VHDL. See the “readme” file in the “ISE_Project”
folder under the “Sample_Code” directory on the CD for more information.
