Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners.
Avnet Design Services
12 of 25
Rev 1.0 06/08/2004
Released
Literature # ADS-xxxx04
3.1 Virtex-II
FPGA
The Virtex-II Development board was designed to support the Virtex-II FPGA in multiple packages and densities. The board
supports three different Virtex-II densities: XC2V1500, XC2V4000 or XC2V6000. The schematic symbol used for the Virtex-
II device indicates the specific I/O pins available in each density (XC2V1500-5FG896C (528 total I/O) in a FF896 fine pitch
BGA package or the XC2V4000/6000-4FF1152C (824 total I/O) in a FF1152 fine pitch package. Configuration information
is provided from two sources; the Xilinx Serial/Parallel Download Connectors (JTAG/SelectMAP), or System ACE MPM
configuration solution.
3.1.1 LVDS
The Virtex-II Evaluation board uses one of the AvBus connectors (P3) to provide up to 38 LVDS pairs. These pairs, labeled
LVDS_IN_P/N(1:11) and LVDS_OUT_P/N(1:27) are matched length. Each pair _P and _N are routed as differential pairs
and are tightly coupled. Each transmit or receive pair should be configured accordingly because by default, the receive pairs
termination resistors are installed on the board. A receive pair can be reconfigured as a transmit pair by removing the
termination resistor or a termination resistor can be installed for a transmit pair to convert it to a receive pair.
3.2 Memory
The Virtex-II Development board is populated with Micron SODIMM DDR memory and Intel StrataFlash
. Additional
memory including FLASH, SDRAM, and SRAM are available with the purchase of the Avnet Communications/Memory
Module.
3.2.1 DDR
SDRAM
The DDR SDRAM consists of one 128 MB DIMM module (expandable to 512 MB), accessible in a 64-bit configuration and
housed in a SODIMM packages. These are SSTL2 Class II interface devices running at a maximum 133 MHz (266 Mbits/S).
By using the Virtex-II Digital Clock Manager (DCM) the onboard 125.00 MHz frequency can be adjusted to support the DDR
SDRAM.
3.2.2 Flash
The FLASH memory consists of one 8 MB device in a 16-bit configuration. The device package is a 56-pin TSOP Type. The
current configuration utilizes 120 nanosecond devices, but the Virtex-II FPGA will support much faster devices.
3.3 Communication
The Virtex-II FPGA has access to an RS232 transceiver for communication purposes. The channel uses a DB9 (P1)
connector and an RS232 transceiver.
3.3.1 RS232
Transceiver
The RS232 transceiver is a 3222 available from Harris/Intersil (ICL3222CA) and Analog Devices (ADM3222). This
transceiver is operating at 3.3V for VCC. The FPGA transmit/receive signals are connected to an I/O voltage selectable
bank of the FPGA (Bank 2). Because the 3222 minimum logic threshold high is 2V, the recommended VCCO for the
FPGA are 2.5V or 3.3V. The internal charge pump creates the RS232 compatible output levels. See Table 5 for RS-232
connector pin assignment.
Signal
Name
DB9 Connector Def.
TX out
2
RX in
3
GND 5
Table 5 - RS232 Connector Pin-out
