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Rev 1.0 06/08/2004
Released
Literature # ADS-xxxx04
2.3 Jumper
Settings
This section provides a description of the jumper settings for the Development board. The board is ready to use out of the
box with the default jumper settings.
JP1 – Configuration mode selection. Use to select the configuration mode for the FPGA. By default, these pins are pulled
low enabling Master Serial mode. Installing jumpers on JP1 will pull the corresponding mode pin high, as indicated in Figure 3.
See the Configuration section of this document or Chapter 3 of the Virtex-II Platform FPGA Handbook for further
information.
JP1
Mo
de
0
Mo
de
1
Mo
de
2
M0
1-2
M1
3-4
M2
5-6
1
0
0
1
1
1
0
1
1
0
1
0
1
0
1
Master Serial
Slave Serial
Master SelectMAP
Slave SelectMAP
Boundary Scan
JP1
Config Mode
Figure 3 – JP1
U25 – Parallel IV connector. See the Boundary scan section of this document for more information
JP2, JP12, & JP13 – Vcco selectable voltages are available on the Virtex-II Development Board to support the FPGAs various
voltage standards. The Virtex-II Development Board provides various selectable I/O voltages for FPGA banks 0,1,4 & 5,
independent of each other, to support the various I/O standards. The I/O voltages available are +3.3V, +2.5V, +1.8V and
+1.5V. JP2 selects I/O voltage for Banks 4&5; JP12 for Bank0, and JP13 for Bank1. Only one jumper should be placed at
each connector. Valid placements, per connector, are 1-2, 3-4, 5-6 or 7-8 as indicated in Figure 4
JP2
3.
3V
2.5
V
1.8
V
2.5V
3-4
1.8V
5-6
1.5V
7-8
Jumper Position
I/O Voltage
3.3V
1-2
1.5
V
Figure 4 - I/O Voltage Selection
JP4 – HSWAP_EN, Enables pull-ups on the Virtex-II I/O pins during configuration. Install a jumper to enable the
configuration pull-ups. Default: Open; pull-ups disabled.
JP5 – Access to temperature sensing diode pins of FPGA (DXP, DXN)
JP6, JP7, & JP8 - The PCI power jumper. When the jumpers are installed, they configure the board for PCI power mode, and
utilizes the +5Vdc from the PCI motherboard.
JP14 – Bank 0 Voltage Reference(Vref) selection. Selects Vref voltage for FPGA banks 0. The reference voltages available are
+1.65V, +1.25V, +.9V, +.75V and +1.5V (half the I/O voltage, and +1.5V which is jumper selected). Jumper 1-2 assigns
+1.5V as Bank0 Vref. Jumper 2-3 assigns half of I/O voltage selected with JP12 as Bank 0 Vref.
JP15 – Bank 1 Voltage Reference(Vref) selection. Selects Vref voltage for FPGA banks 1. The reference voltages available are
+1.65V, +1.25V, +.9V, +.75V and +1.5V (half the I/O voltage, and +1.5V which is jumper selected). Jumper 1-2 assigns
+1.5V as Bank1 Vref. Jumper 2-3 assigns half of I/O voltage selected with JP13 as Bank 1 Vref.
