Avnet Xilinx Virtex-II User Manual Download Page 7

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Avnet Design Services

7 of 25

Rev 1.0 06/08/2004

Released

Literature # ADS-xxxx04

2.2.4 Configuration

Modes

Upon power-up the FPGA will be enabled in a configuration mode defined by jumper header JP1. The default

configuration mode is “Master-Serial” mode, which will allow the FPGA to be programmed from the System ACE MPM.

The System ACE has been programmed with basic test application code to test the on-board peripherals. Section 4.0

describes the various tests included with the System ACE. Table 3 describes the various configuration modes available by

setting the appropriate jumper/mode select.

Configuration

Mode

JP1

(1-2)

JP1

(3-4)

JP1

(5-6)

* Master serial

OPEN

Slave serial

JUMPERED

Master SelectMAP

OPEN

JUMPERED

Slave SelectMAP

JUMPERED

OPEN

Boundary-scan JUMPERED OPEN JUMPERED

* = Default assembled state

Table 3 - Virtex-II Power-up Configuration Modes

JP1

Mode

JP1

Mode

Master Serial Mode:

No Jumpers on JP2

Master SelectMAP mode:

place jumpers at JP2

positions 1-2 & 3-4.

JP1

Mode

For Boundary Scan mode,

place jumpers at JP2

positions 1-2 & 5-6.

Summary of Contents for Xilinx Virtex-II

Page 1: ...the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Design Services 1 of 25 Rev 1 0 06 08 2004 Released Literature ADS xxxx04 user s guide Xilinx Virtex II Development Kit ...

Page 2: ...2 4 Configuration Modes 7 2 2 5 JTAG Chain 8 2 3 Jumper Settings 9 3 0 Hardware 11 3 1 Virtex II FPGA 12 3 1 1 LVDS 12 3 2 Memory 12 3 2 1 DDR SDRAM 12 3 2 2 Flash 12 3 3 Communication 12 3 3 1 RS232 Transceiver 12 3 4 LED 13 3 5 Dip Switches 13 3 6 Connectors 13 3 6 1 General I O Interface 14 3 6 1 1 LVDS 16 3 6 2 Memory Expansion Connector Interface 17 3 6 3 Auxiliary Connectors Available only w...

Page 3: ...ctor J4 23 Tables Table 1 Ordering Information 5 Table 2 JTAG Headers JTAG3 JTAG4 Pin Out 6 Table 3 Virtex II Power up Configuration Modes 7 Table 4 JTAG Boundary Scan Description Language BSDL files 8 Table 5 RS232 Connector Pin out 12 Table 6 LED Pin Assignment the FPGA 13 Table 7 Switch Pin Assignment the FPGA 13 Table 8 General I O AvBus Connector P2 P3 15 Table 9 Low Voltage Differential Sign...

Page 4: ...ed multipliers advanced digital clock management built in impedance matching IP immersion and other exciting features can be implemented with advanced Xilinx design tools Demonstration VHDL code is included with the kit to exercise standard peripherals on the evaluation board for a quick start to device familiarization 1 2 Features FPGA Xilinx Virtex II XC2V1500 FF896 Board I O Connectors Four 140...

Page 5: ... Kit populated with an XC2V4000 device high current power supply ADS V2 MB DEV4000XP Xilinx Virtex II Development Kit bundled with Communications Memory Module MicroBlaze Core License high current power supply ADS XLX V2 DEV6000XP Xilinx Virtex II Development Kit populated with an XC2V6000 device high current power supply ADS V2 MB DEV6000XP Xilinx Virtex II Development Kit bundled with Communicat...

Page 6: ...e pin out of the JTAG4 connector 2 2 2 System ACE MPM Configuration The System ACE Multi Package Module MPM is a configuration solution for high density FPGAs Configuration files for the target FPGA are programmed into the MPM using the iMPACT software and a JTAG download cable The MPM is a combination of three devices a configuration PROM a small Virtex E FPGA and an industry standard Flash devic...

Page 7: ...the on board peripherals Section 4 0 describes the various tests included with the System ACE Table 3 describes the various configuration modes available by setting the appropriate jumper mode select Configuration Mode M2 JP1 1 2 M1 JP1 3 4 M0 JP1 5 6 Master serial OPEN OPEN OPEN Slave serial JUMPERED JUMPERED JUMPERED Master SelectMAP OPEN JUMPERED JUMPERED Slave SelectMAP JUMPERED JUMPERED OPEN ...

Page 8: ...SDL files for each device in the chain are given on Table 4 Bypassed Virtex II JTAG Scan Chain Path J T A G C O N N FPGA PROM No 1 PROM No 5 GEN IO CONN MEM CONN U1 J3 P2 P4 FPGA_TDI U5 PCIX_TDO J T A G C O N N MEM IO GEN IO 1 PCI PCIX FPGA System ACE J2 FPGA TDO AV1_TDI AV1_TDO JTAG_TDO U25 Jumper selectable w JP100 PROM No 1 JP100 JTAG Chain Selection JTAG_TDI AV2_TDI AV2_TDO Figure 2 JTAG Chain...

Page 9: ...A banks 0 1 4 5 independent of each other to support the various I O standards The I O voltages available are 3 3V 2 5V 1 8V and 1 5V JP2 selects I O voltage for Banks 4 5 JP12 for Bank0 and JP13 for Bank1 Only one jumper should be placed at each connector Valid placements per connector are 1 2 3 4 5 6 or 7 8 as indicated in Figure 4 JP2 3 3V 2 5V 1 8V 2 5V 3 4 1 8V 5 6 1 5V 7 8 Jumper Position I ...

Page 10: ...all jumpers across pins 1 2 pins 3 4 and pins 5 6 to add the AvBus connector labeled P3 on to the standalone chain These settings are described in detail in the Hardware section of this manual see section 3 11 Default Installed across pins 2 3 standalone chain mode JP101 JTAG TCK Enable for JTAG Connector P2 Default Closed JP102 JTAG TCK Enable for JTAG Connector P4 Default Closed JP103 System ACE...

Page 11: ... the user to add via the connector interfaces evaluation boards containing their desired unique circuit functionality to integrate The capability to install evaluation boards onto the Virtex II Development board allows FPGA integration between multiple platforms and I O standards if desired The block diagram of the development board is shown in Figure 5 PCI PCI X JTAG SelectMAP System ACE MPM Osci...

Page 12: ...smit pair to convert it to a receive pair 3 2 Memory The Virtex II Development board is populated with Micron SODIMM DDR memory and Intel StrataFlash Additional memory including FLASH SDRAM and SRAM are available with the purchase of the Avnet Communications Memory Module 3 2 1 DDR SDRAM The DDR SDRAM consists of one 128 MB DIMM module expandable to 512 MB accessible in a 64 bit configuration and ...

Page 13: ...500 Pin 4000 Pin Pin Description SWITCH0 AJ1 AL3 SWITCH0 SWITCH1 AH1 AK3 SWITCH1 SWITCH2 AG3 AJ5 SWITCH2 SWITCH3 AF4 AH6 SWITCH3 SWITCH4 AE5 AG7 SWITCH4 SWITCH5 AD5 AF7 SWITCH5 SWITCH6 AD9 AF11 SWITCH6 SWITCH7 AC9 AE11 SWITCH7 Table 7 Switch Pin Assignment the FPGA 3 6 Connectors The Virtex II Development board is an Avalon compliant motherboard that incorporates board to board connectors to suppo...

Page 14: ...IO2_17 GEN_IO1_19 85 15 GEN_IO1_18 GEN_IO2_19 85 15 GEN_IO2_18 GEN_IO1_20 86 16 GND GEN_IO2_20 86 16 GND GND 87 17 GEN_IO1_21 GND 87 17 GEN_IO2_21 GEN_IO1_23 88 18 GEN_IO1_22 GEN_IO2_23 88 18 GEN_IO2_22 GEN_IO1_24 89 19 GND GEN_IO2_24 89 19 GND 3 3V 90 20 GEN_IO1_25 3 3V 90 20 GEN_IO2_25 GEN_IO1_27 91 21 GEN_IO1_26 GEN_IO2_27 91 21 GEN_IO2_26 GEN_IO1_28 92 22 GND GEN_IO2_28 92 22 GND GND 93 23 GEN...

Page 15: ...2_70 GEN_IO1_72 125 55 GND GEN_IO2_72 125 55 GND 3 3V 126 56 GEN_IO1_73 3 3V 126 56 GEN_IO2_73 GEN_IO1_75 127 57 GEN_IO1_74 GEN_IO2_75 127 57 GEN_IO2_74 GEN_IO1_76 128 58 GND GEN_IO2_76 128 58 GND GND 129 59 GEN_IO1_77 GND 129 59 GEN_IO2_77 GEN_IO1_79 130 60 GEN_IO1_78 GEN_IO2_79 130 60 GEN_IO2_78 GEN_IO1_80 131 61 5V GEN_IO2_80 131 61 5V GND 132 62 GEN_IO1_81 GND 132 62 GEN_IO2_81 GEN_IO1_83 133 ...

Page 16: ...GEN_IO2_8 2 16 GEN_IO2_60 GEN_IO2_6 2 GEN_IO2_11 GEN_IO2_61 GEN_IO2_9 GEN_IO2_12 3 17 GEN_IO2_62 GEN_IO2_10 3 GEN_IO2_15 GEN_IO2_63 GEN_IO2_13 GEN_IO2_16 4 18 GEN_IO2_64 GEN_IO2_14 4 GEN_IO2_19 GEN_IO2_65 GEN_IO2_17 GEN_IO2_20 5 19 GEN_IO2_66 GEN_IO2_18 5 GEN_IO2_23 GEN_IO2_67 GEN_IO2_21 GEN_IO2_24 6 20 GEN_IO2_68 GEN_IO2_22 6 GEN_IO2_27 GEN_IO2_69 GEN_IO2_25 GEN_IO2_28 7 21 GEN_IO2_70 GEN_IO2_26 ...

Page 17: ...V44 80 10 GND GND 81 11 ADDR_AV13 GND 81 11 DATA_AV45 ADDR_AV15 82 12 ADDR_AV14 DATA_AV47 82 12 DATA_AV46 ADDR_AV16 83 13 5V DATA_AV48 83 13 5V GND 84 14 ADDR_AV17 GND 84 14 DATA_AV49 ADDR_AV19 85 15 ADDR_AV18 DATA_AV51 85 15 DATA_AV50 ADDR_AV20 86 16 GND DATA_AV52 86 16 GND GND 87 17 ADDR_AV21 GND 87 17 DATA_AV53 ADDR_AV23 88 18 ADDR_AV22 DATA_AV55 88 18 DATA_AV54 ADDR_AV24 89 19 GND DATA_AV56 89...

Page 18: ...3 53 SDRAM_CS 3 3V 123 53 MEM_IO_37 SDRAM_WE 124 54 SDRAM_CAS MEM_IO_39 124 54 MEM_IO_38 SDRAM_CLK 125 55 GND MEM_IO_40 125 55 GND 3 3V 126 56 SDRAM_RAS GND 126 56 MEM_IO_41 SDRAM_BYTE0 127 57 SDRAM_CLKEN MEM_IO_43 127 57 MEM_IO_42 SDRAM_BYTE1 128 58 GND MEM_IO_44 128 58 5V GND 129 59 SDRAM_BYTE2 GND 129 59 MEM_IO_45 MEM_IO_0 130 60 SDRAM_BYTE3 MEM_IO_47 130 60 MEM_IO_46 MEM_IO_1 131 61 5V MEM_IO_...

Page 19: ...15 82 12 V25_IO_14 V33_IO_15 82 12 V33_IO_14 V25_IO_16 83 13 5V V33_IO_16 83 13 5V GND 84 14 V25_IO_17 GND 84 14 V33_IO_17 V25_IO_19 85 15 V25_IO_18 V33_IO_19 85 15 V33_IO_18 V25_IO_20 86 16 GND V33_IO_20 86 16 GND GND 87 17 V25_IO_21 GND 87 17 V33_IO_21 V25_IO_23 88 18 V25_IO_22 V33_IO_23 88 18 V33_IO_22 V25_IO_24 89 19 GND V33_IO_24 89 19 GND 3 3V 90 20 V25_IO_25 3 3V 90 20 V33_IO_25 V25_IO_27 9...

Page 20: ... 3V 126 56 V33_IO_73 V25_IO_75 127 57 V25_IO_74 V33_IO_75 127 57 V33_IO_74 V25_IO_76 128 58 GND V33_IO_76 128 58 GND GND 129 59 V25_IO_77 GND 129 59 V33_IO_77 V25_IO_79 130 60 V25_IO_78 V33_IO_79 130 60 V33_IO_78 V25_IO_80 131 61 5V V33_IO_80 131 61 5V GND 132 62 V25_IO_81 GND 132 62 V33_IO_81 V25_IO_83 133 63 V25_IO_82 V33_IO_83 133 63 V33_IO_82 V25_IO_84 134 64 GND V33_IO_84 134 64 GND GND 135 6...

Page 21: ... II data rates It is intended for example to be an integral interface to a high end workstation as part of the final product That is the final product implements 64 bit PCI PCI X It is not intended as a low bandwidth control port to allow designers the convenience of placing the board in a PC at their desk for emulation If the end application is a 3 3V OR 5V 64 66 100 PCI PCI X then the customer w...

Page 22: ... AD 06 A54 AD 40 A85 AD 25 B24 AD 05 B55 AD 39 B86 GND A24 AD 04 A55 AD 38 A86 3 3V B25 AD 03 B56 AD 37 B87 AD 24 A25 GND A56 GND A87 C BE 3 B26 GND B57 n c B88 IDSEL A26 AD 02 A57 AD 36 A88 AD 23 B27 AD 01 B58 AD 35 B89 3 3V A27 AD 00 A58 AD 34 A89 GND B28 n c B59 AD 33 B90 AD 22 A28 n c A59 GND A90 AD 21 B29 ACK64 B60 GND B91 AD 20 A29 REQ64 A60 AD 32 A91 AD 19 B30 5V B61 reserved B92 GND A30 5V...

Page 23: ...emiconductor LP3966 ADJ parts provide 2 5V and 1 5V The barrel connector J4 is shown below in Figure 7 It should be noted that there is no protection for reverse power supply polarity so take necessary precautions to ensure that the center pin is 4 5V 5 5V and the ring is ground φ0 076 in 1 93 mm pin diameter φ0 25 in 6 3 mm housing diameter 5 Volts GND Figure 7 Barrel Power Connector J4 3 10 1 FP...

Page 24: ...cribes the test designs that are programmed into the System ACE MPM device These designs are used to test the functionality of the board Some of the tests require additional test apparatus to perform the testing If the System ACE has been erased the MPM file containing the test designs is on the Virtex II Development Kit CD Most of the test designs use a terminal session as the user interface Usin...

Page 25: ...d 5V PCI to connect the 5V input from the PCI slot to the 5V rail Then plug the board into a PCI slot do not hot plug the board the PC must be powered off Turn on the PC At this time the user should be able to read the configuration space of the board over the PCI bus and perform single transfers to BAR0 and BAR1 There is a software program in the Utilities folder on the CD called the ADS PCI Util...

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