Avnet UltraZed-EG, Hardware User'S Manual

Page: 9 / 47

Version 1.0 Page 9
NOTE: (U24 or U25 indicates DDR4 Device Reference Designator)
2.2.2 Dual Parallel (x8) QSPI Flash
The UltraZed-EG SOM features two 4-bit SPI (quad-SPI) serial NOR flash devices organized in a dual
parallel configuration. The
Micron MT25QU256ABAIEW7-0SIT QSPI Flash devices are used on the
UltraZed-EG SOM. The Multi-I/O SPI Flash memory is used to provide non-volatile boot, application code,
and data storage. It can be used to initialize the PS subsystem as well as configure the PL subsystem
(bitstream).
The Quad-SPI Flash connects to the Zynq Ult MPSoC PS QSPI interface. This requires connection
to specific pins in MIO Bank 500, specifically MIO[0:12] as outlined in the Zynq Ult TRM (Technical
Reference Manual, UG1085). Quad-SPI feedback mode is used, thus the CLK_FOR_LPBK signal tied to
MIO[6] is left floating. This allows a QSPI clock frequency greater than FQSPICLK2.
The Zynq Ult MPSoC peripheral used to control the QSPI flash devices is named QSPI. The
QSPI devices can be operated up to 166MHz depending on the operating mode and the possible
performance of the QSPI controller in the MPSoC. The QSPI flash devices are physically connected to the
QSPI controller in the PS of the Zynq Ult MPSoC via Bank 500.
PS_DDR_DM0 DDR Data Byte 0 Data Mask AA14 U24-E7
PS_DDR_DQS0_P DDR Data Byte 0 Data Strobe Pair AC14 U24-G3
PS_DDR_DQS0_N DDR Data Byte 0 Data Strobe Pair AD14 U24-F3
PS_DDR_DQ8 DDR Data Byte 1 AC16 U24-A3
PS_DDR_DQ9 DDR Data Byte 1 AB16 U24-B8
PS_DDR_DQ10 DDR Data Byte 1 AD16 U24-C3
PS_DDR_DQ11 DDR Data Byte 1 AE16 U24-C7
PS_DDR_DQ12 DDR Data Byte 1 AE19 U24-C2
PS_DDR_DQ13 DDR Data Byte 1 AD18 U24-C8
PS_DDR_DQ14 DDR Data Byte 1 AB18 U24-D3
PS_DDR_DQ15 DDR Data Byte 1 AC18 U24-D7
PS_DDR_DM1 DDR Data Byte 1 Data Mask AB17 U24-E2
PS_DDR_DQS1_P DDR Data Byte 1 Data Strobe Pair AD17 U24-B7
PS_DDR_DQS1_N DDR Data Byte 1 Data Strobe Pair AE17 U24-A7
PS_DDR_DQ16 DDR Data Byte 2 W18 U25-G2
PS_DDR_DQ17 DDR Data Byte 2 Y19 U25-F7
PS_DDR_DQ18 DDR Data Byte 2 AA19 U25-H3
PS_DDR_DQ19 DDR Data Byte 2 W16 U25-H7
PS_DDR_DQ20 DDR Data Byte 2 AA18 U25-H2
PS_DDR_DQ21 DDR Data Byte 2 AA15 U25-H8
PS_DDR_DQ22 DDR Data Byte 2 Y16 U25-J3
PS_DDR_DQ23 DDR Data Byte 2 Y15 U25-J7
PS_DDR_DM2 DDR Data Byte 2 Data Mask W17 U25-E7
PS_DDR_DQS2_P DDR Data Byte 2 Data Strobe Pair Y17 U25-G3
PS_DDR_DQS2_N DDR Data Byte 2 Data Strobe Pair AA17 U25-F3
PS_DDR_DQ24 DDR Data Byte 3 AE20 U25-A3
PS_DDR_DQ25 DDR Data Byte 3 AD19 U25-B8
PS_DDR_DQ26 DDR Data Byte 3 AB20 U25-C3
PS_DDR_DQ27 DDR Data Byte 3 AC19 U25-C7
PS_DDR_DQ28 DDR Data Byte 3 AE21 U25-C2
PS_DDR_DQ29 DDR Data Byte 3 AB21 U25-C8
PS_DDR_DQ30 DDR Data Byte 3 AE22 U25-D3
PS_DDR_DQ31 DDR Data Byte 3 AD22 U25-D7
PS_DDR_DM3 DDR Data Byte 3 Data Mask AD21 U25-E2
PS_DDR_DQS3_P DDR Data Byte 3 Data Strobe Pair AC20 U25-B7
PS_DDR_DQS3_N DDR Data Byte 3 Data Strobe Pair AC21 U25-A7
+DDR4_VREF DDR Reference voltage - VREFCA
+DDR4_VTT DDR Termination voltage - -