Avnet UltraZed-EG Hardware User'S Manual Download Page 12 | Manualshive

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Version 1.0

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The UltraZed-EG SOM is capable of implementing up to a PCIe x4 interface as the physical design of the
GTRs are each length tuned from the Zynq Ult MPSoC  device to the JX3 connector taking  into
account the device package delays. The MPSoC device net length report provided by Xilinx and the PCB
net  length  report  provided  by  Avnet  can  be  used  to  determine  the  required  delay  for  each  implemented
interface on the end-user carrier card.

The table below shows the connections between the Zynq Ult MPSoC device and the JX3 Micro
Header.

Table 4

– Bank 505 GTR Pin Assignments

PS IO NAME

PACKAGE PIN NUMBER

NET NAME

JX3 CONNECTOR

PS_MGTRRXN0_505

M25

GTR_RX0_N

JX3.28

PS_MGTRRXN1_505

H25

GTR_RX1_N

JX3.20

PS_MGTRRXN2_505

D25

GTR_RX2_N

JX3.12

PS_MGTRRXN3_505

B25

GTR_RX3_N

JX3.6

PS_MGTRRXP0_505

M24

GTR_RX0_P

JX3.26

PS_MGTRRXP1_505

H24

GTR_RX1_P

JX3.18

PS_MGTRRXP2_505

D24

GTR_RX2_P

JX3.10

PS_MGTRRXP3_505

B24

GTR_RX3_P

JX3.4

PS_MGTRTXN0_505

K25

GTR_TX0_N

JX3.23

PS_MGTRTXN1_505

F25

GTR_TX1_N

JX3.15

PS_MGTRTXN2_505

C23

GTR_TX2_N

JX3.9

PS_MGTRTXN3_505

A23

GTR_TX3_N

JX3.3

PS_MGTRTXP0_505

K24

GTR_TX0_P

JX3.21

PS_MGTRTXP1_505

F24

GTR_TX1_P

JX3.13

PS_MGTRTXP2_505

C22

GTR_TX2_P

JX3.7

PS_MGTRTXP3_505

A22

GTR_TX3_P

JX3.1

PS_MGTREFCLK0N_505

L23

GTR_REFCLK0_N

JX3.40

PS_MGTREFCLK0P_505

L22

GTR_REFCLK0_P

JX3.38

PS_MGTREFCLK1N_505

J23

GTR_REFCLK1_N

JX3.35

PS_MGTREFCLK1P_505

J22

GTR_REFCLK1_P

JX3.33

PS_MGTREFCLK2N_505

G23

GTR_REFCLK2_N

JX3.34

PS_MGTREFCLK2P_505

G22

GTR_REFCLK2_P

JX3.32

PS_MGTREFCLK3N_505

E23

GTR_REFCLK3_N

JX3.29

PS_MGTREFCLK3P_505

E22

GTR_REFCLK3_P

JX3.27

PS_MGTRREF_505

K22

GTR_RREF

-

2.3.1

SFVA625 Device Package Delay Compensation for GTR Transceiver Interface

The Zynq Ult MPSoC device package delay is accommodated for in the layout of the each of the
GTR transceiver signal trace lengths. The average of min and max values for package delay is utilized to
compensate for the flight time caused by the delay associated with this package.

2.4 USB 2.0 OTG

The Zynq Ult MPSoC contains a hardened PS USB 2.0 controller. The UltraZed-EG SOM takes
advantage of one of the two available PS USB 2.0 controllers to provide USB 2.0 On-The-Go signalling to
the JX3 connector.

An external PHY with an 8-bit ULPI interface is implemented. A Microchip USB3320 Standalone USB
Transceiver Chip is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting
speeds of up to 480Mbs. VDDIO for this device can be 1.8V or 3.3V, and on the UltraZed-EG SOM VDDIO
is powered at 1.8V. The PHY is connected to MIO Bank 502 which is also powered at 1.8V. This is critical

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Summary of Contents for UltraZed-EG

Page 1: ...Accelerate Success Technology UltraZed EG SOM Hardware User Guide Version 1 0 ...

Page 2: ...rol Document Version Version 1 0 Document Date December 7 2016 Document Author s Donny Saveski Document Classification Public Document Distribution Public Prior Version History Version Date Comment 1 0 12 7 16 Initial Release Comments ...

Page 3: ... 3 SFVA625 Device Package Delay Compensation for 10 100 1000 Ethernet Interface 16 2 6 I2C I O Expander 17 2 7 I2C Switch Multiplexer 18 2 7 1 End User Carrier Card I2C Interface 19 2 7 2 PMBUS Interface 20 2 8 I2C EEPROM 21 2 9 PS General Purpose Interrupt 21 2 10 User I O 21 2 10 1 PS MIO User Pins 21 2 10 2 PL IO User Pins 22 2 11 Clock Sources 22 2 12 Control Signal Sources 23 2 12 1 Power On ...

Page 4: ...s 37 2 15 4 PCB Bypass Decoupling Strategy 40 2 15 5 Power Estimation 41 2 15 6 System Monitor SYSMON 41 2 15 7 Battery Backup Device Secure Boot Encryption Key 42 2 15 8 Thermal Management Heatsink and Fan Assembly 43 3 Zynq UltraScale MPSoC I O Bank Allocation 44 3 1 PS MIO Bank Allocation 44 3 2 Zynq UltraScale MPSoC Bank Voltages 45 4 Mechanical 46 ...

Page 5: ...s o Gigabit Ethernet PHY Connector required on End User Carrier Card o USB 2 0 ULPI PHY Connector required on End User Carrier Card o One 100 pin JX Micro Header o Two 140 pin JX Micro Headers o I2C I O Expander o Two Channel I2C Switch MUX PS Reference Clock Input o 33 333 MHz OSC Power o On Board 5 Output Voltage Regulators o Full Power Sequencing Pre Programmed o Support for Zynq UltraScale PS ...

Page 6: ...GND 31 VCCO 6 VIN 3 SYSMON 4 PMBus 3 SOM_RESET_IN CC_RESET_OUT SOM_PG_OUT Voltage Regulators Input 5 12V Outputs 0 6V 0 85V 1 0V 1 2V 1 25V 1 8V 2 5V 3 3V 100 Pin Connector JX3 Signal 65 GND 19 GTRAVCC 3 GTRAVTT 2 Sense 6 PS_VBATT CC_SDA CC_SCL CC_INT VCCO_PSIO_501 DDR4 2GB x32 Dual QSPI 64MB USB 2 0 ULPI PHY Ethernet RGMII PHY MIO 13 22 eMMC 8GB x8 26 5 10 16 8 HP I O 66 HD I O 24 INT MIO 23 PMBu...

Page 7: ...T40A512M16JY 083E IT B 96 pin BGA package DDR4 memory components creating a 512M x 32 bit interface totalling 2 GB of random access memory The DDR4 memory is connected to the hard memory controller in the PS of the Zynq UltraScale MPSoC via its Bank 504 PS Memory Interface The Bank 504 PS Memory Interface incorporates both the DDR controller and the associated PHY including its own set of IOs Spee...

Page 8: ...DDR_A14 DDR Address RAS Input AC24 L2 PS_DDR_A15 DDR Address CAS Input AD23 M8 PS_DDR_A16 DDR Address WE_N Input Y21 L8 PS_DDR_BA0 DDR Bank Address Inputs W22 N2 PS_DDR_BA1 DDR Bank Address Inputs V20 N8 PS_DDR_BG0 DDR Bank Group Address Inputs V19 M2 PS_DDR_CKE0 DDR Clock Enable Input T24 K2 PS_DDR_CK0_P DDR Clock Device 0 Pair AA23 K7 PS_DDR_CK0_N DDR Clock Device 0 Pair AA24 K8 PS_DDR_CS0_N DDR...

Page 9: ...DDR Data Byte 0 Data Strobe Pair AD14 U24 F3 PS_DDR_DQ8 DDR Data Byte 1 AC16 U24 A3 PS_DDR_DQ9 DDR Data Byte 1 AB16 U24 B8 PS_DDR_DQ10 DDR Data Byte 1 AD16 U24 C3 PS_DDR_DQ11 DDR Data Byte 1 AE16 U24 C7 PS_DDR_DQ12 DDR Data Byte 1 AE19 U24 C2 PS_DDR_DQ13 DDR Data Byte 1 AD18 U24 C8 PS_DDR_DQ14 DDR Data Byte 1 AB18 U24 D3 PS_DDR_DQ15 DDR Data Byte 1 AC18 U24 D7 PS_DDR_DM1 DDR Data Byte 1 Data Mask ...

Page 10: ...S of the Zynq UltraScale MPSoC via Bank 500 The eMMC I O has direct connections to the Zynq UltraScale MIO through the PS_MIO 13 22 pins The UltraZed EG SOM end user is capable of issuing a soft reset P0_EMMC0_RST_N to the eMMC flash device via an on board two wire serial interface The active low reset is assigned to Port 0 of the Texas Instruments TCA9534 I O expander The I O expander is attached...

Page 11: ...faces The Zynq UltraScale MPSoC device package delay is accommodated for in the layout of the each of the memory interfaces signal trace lengths The average of min and max values for package delay is utilized to compensate for the flight time caused by the delay associated with this package 2 3 GTR Transceivers The UltraZed EG SOM has four multi gigabit transceiver lanes that reside on Bank 505 of...

Page 12: ...PS_MGTRTXP3_505 A22 GTR_TX3_P JX3 1 PS_MGTREFCLK0N_505 L23 GTR_REFCLK0_N JX3 40 PS_MGTREFCLK0P_505 L22 GTR_REFCLK0_P JX3 38 PS_MGTREFCLK1N_505 J23 GTR_REFCLK1_N JX3 35 PS_MGTREFCLK1P_505 J22 GTR_REFCLK1_P JX3 33 PS_MGTREFCLK2N_505 G23 GTR_REFCLK2_N JX3 34 PS_MGTREFCLK2P_505 G22 GTR_REFCLK2_P JX3 32 PS_MGTREFCLK3N_505 E23 GTR_REFCLK3_N JX3 29 PS_MGTREFCLK3P_505 E22 GTR_REFCLK3_P JX3 27 PS_MGTRREF_5...

Page 13: ...Mode OTG or Device Mode With a standard connection to an end user carrier card no power supply used to provide USB power to the connector the device will operate in Device Mode Using the USB_OTG_CPEN signal on JX3 allows the user to control an external power source for USB_OTG_VBUS on the end user carrier card Other considerations need to be made to accommodate Host Mode Refer to the Avnet UltraZe...

Page 14: ...PHY_LED1 52 The next table shows the pin assignments to Bank 502 of the Zynq UltraScale MPSoC device for the 10 100 1000 Ethernet Port Table 8 10 100 1000 Ethernet MPSoC Pin Assignments Ethernet PHY Signals MPSoC Pin MIO77_GEM3_MDIO H19 MIO76_GEM3_MDC H20 MIO74_GEM3_RX_D3 G20 MIO73_GEM3_RX_D2 F20 MIO72_GEM3_RX_D1 E20 MIO71_GEM3_RX_D0 E19 MIO75_GEM3_RX_CTL F19 MIO70_GEM3_RX_CLK C20 MIO68_GEM3_TX_D3...

Page 15: ... VDDA1P8 VDDA2P5 VDD1P0 INT PWDN 2 2K 1 8V 1 8V 1 8V 2 5V 1 0V 2 2K 1 8V JTAG TDI TDO TMS TCK RX_ER GPIO0 COL GPIO1 RX_CTRL 1 8V 1 8V 0 0 0 3 3V 2 2K 1 8V Figure 6 10 100 1000 Ethernet Interface Implementation 2 5 1 Ethernet PHY Strapping Resistors The Texas Instruments DP83867 device that is utilized to implement the 10 100 1000 Ethernet PHY functionality contains many setup options that can be i...

Page 16: ... 0 for Tri Mode Ethernet 2 5 2 Ethernet PHY LEDs The UltraZed EG SOM contains a single Ethernet PHY controlled LED the LINK LED On board the end user carrier card or within the RJ45 Ethernet Jack on the end user carrier card two additional Ethernet PHY controlled LED signal are provided SPEED and ACTIVITY SPEED and ACTIVITY LEDs need to be implemented on the end user carrier card Care must be take...

Page 17: ...6 P PORT P2_GEM3_RST_N P3 7 P PORT P3_GEM3_PWDN_N GND 8 GROUND GND P4 9 P PORT P4_I2CMUX_INT_N P5 10 P PORT P5_PMBUS_ALERT_N P6 11 P PORT P6_I2CMUX_RST_N P7 12 P PORT P7_CC_RST_N INT_N 13 INTERRUPT MIO23_INT_N SCL 14 SERIAL CLOCK MIO24_I2C1_SCL SDA 15 SERIAL DATA MIO25_I2C1_SDA VCC 16 POWER VCCO_PSIO0_500 Table 12 TCA9534 P Ports Function I O NAME FUNCTION DIRECTION Active State NET NAME P0 eMMC S...

Page 18: ...l as any device that may exist on the end user carrier card PMBUS through the JX2 connector The two wire serial interface on the Zynq UltraScale MPSoC is used as the serial source for to the TCA9543A The following table shows the connections to the TCA9543A device Table 14 Texas Instruments TCA9543A Pin Mapping SWITCH MUX NAME SWITCH MUX PIN FUNCTION NET NAME A0 1 ADDRESS GND A1 2 ADDRESS GND RESE...

Page 19: ...ces on the UltraZed EG SOM Table 16 Carrier Card I2C Net Mapping Switch MUX NAME Switch MUX PIN FUNCTION NET NAME JX3 CONNECTOR INT0_N 4 INTERRUPT0 CC_INT_N JX3 68 SD0 5 SERIAL DATA0 CC_SDA JX3 41 SC0 6 SERIAL CLOCK0 CC_SCL JX3 44 Switch MUX Channel Usage Notes Master Channel SDA SCL INT This channel is connected to the PS I2C port MIO 24 25 and operated at 1 8V The master INT_N output is connecte...

Page 20: ...PMBus can monitor control the end user carrier card PMBus voltage regulators as well If not used the UltraZed EG SOM PMBus interface must be left unconnected on the end user carrier cards so that the UltraZed EG SOM can still control monitor its on board PMBus regulators Table 17 PMBUS JX2 Connector Mapping PMBUS NAME JX2 CONNECTOR PMBUS_SDA JX2 11 PMBUS_SCL JX2 12 P5_PMBUS_ALERT_N JX2 35 The foll...

Page 21: ...PROM Please see the appropriate device datasheet for further details regarding transactions to and from this device Figure 11 I2C EEPROM Addressing 2 9 PS General Purpose Interrupt The UltraZed EG SOM contains a general purpose interrupt IO that is attached to PS MIO 23 This interrupt signal will contain a pull up to VCCO_PSIO0_500 The interrupt output INT of the Texas Instruments TCA9534 device i...

Page 22: ...voltage range for these high performance banks are 1 0V to 1 8V Use of these signals for various interfaces depends on the bank voltages assigned The end user carrier card is responsible for providing the appropriate bank voltages to the VCCO pins for Bank 26 Bank 64 Bank 65 and Bank 66 depending on what interface is being implemented PL I O Bank 64 Bank 65 and 66 contains 52 I O per bank capable ...

Page 23: ...table to the circuitry on the end user carrier card that requires this reset signal The active low reset P7_CC_RST_N is assigned to Port 7 of the Texas Instruments TCA9534 I O expander The I O expander is attached to an I2C peripheral on the Zynq UltraScale device For further information on the I O expander and its connections please locate the I O expander section within this hardware user guide ...

Page 24: ... from lockdown the device either needs to be power cycled or PS_POR_B needs to be asserted 2 13 Expansion Headers 2 13 1 Micro Headers The UltraZed EG SOM features three Micro Headers for connection to end user carrier cards The three Micro Headers consist of two 140 pin connectors and one 100 pin connector The JX1 and JX2 connectors are the main interface to PL signals for the end user carrier ca...

Page 25: ...le 23 Micro Header JX2 Summary Micro Header JX2 Interface Signal Name Source Pins PL Bank 26 Single Ended I Os or Differential Input Pairs Zynq UltraScale Bank 26 24 Bank 65 Single Ended I Os Zynq UltraScale Bank 65 2 Bank 66 Single Ended I Os Zynq UltraScale Bank 66 4 Bank 65 Differential Pair I Os Zynq UltraScale Bank 65 12 Bank 66 Differential Pair I Os Zynq UltraScale Bank 66 48 Control PMBUS ...

Page 26: ...tor Table 25 JX1 Connector Master Table Zynq Pin Number UltraZed EG Net Name JX1 Pin Number UltraZed EG Net Name Zynq Pin Number K16 JTAG_TCK 1 2 JTAG_TMS L18 L17 JTAG_TDO 3 4 JTAG_TDI L15 L6 P5 U4 VCCO_HP_65 5 6 VCCO_HP_64 AA6 AB9 V7 L6 P5 U4 VCCO_HP_65 7 8 JX1_HP_DP_01_P Y7 AB8 JX1_HP_DP_00_P 9 10 JX1_HP_DP_01_N AA7 AB7 JX1_HP_DP_00_N 11 12 VCCO_HP_64 AA6 AB9 V7 L6 P5 U4 VCCO_HP_65 13 14 JX1_HP_...

Page 27: ...5 W6 JX1_HP_DP_20_GC_P 69 70 JX1_HP_DP_21_GC_N AA5 Y6 JX1_HP_DP_20_GC_N 71 72 GND N A N A GND 73 74 JX1_HP_DP_23_P W8 AD2 JX1_HP_DP_22_P 75 76 JX1_HP_DP_23_N W7 AE2 JX1_HP_DP_22_N 77 78 GND N A N A GND 79 80 JX1_HP_DP_25_P R7 T5 JX1_HP_DP_24_P 81 82 JX1_HP_DP_25_N T7 T4 JX1_HP_DP_24_N 83 84 GND N A N A GND 85 86 JX1_HP_DP_27_P T3 U6 JX1_HP_DP_26_P 87 88 JX1_HP_DP_27_N U2 U5 JX1_HP_DP_26_N 89 90 GN...

Page 28: ...ND 5 6 GND N A H10 JX2_HD_SE_00_P 7 8 JX2_HD_SE_01_P C10 H9 JX2_HD_SE_00_N 9 10 JX2_HD_SE_01_N B10 N A PMBus_SDA 11 12 PMBus_SCL N A B11 JX2_HD_SE_02_P 13 14 JX2_HD_SE_03_P B12 A10 JX2_HD_SE_02_N 15 16 JX2_HD_SE_03_N A12 D5 E8 G4 VCCO_HP_66 17 18 VCCO_HD_26 D10 F11 E11 JX2_HD_SE_04_GC_P 19 20 JX2_HD_SE_05_GC_P F9 E10 JX2_HD_SE_04_GC_N 21 22 JX2_HD_SE_05_GC_N E9 D5 E8 G4 VCCO_HP_66 23 24 VCCO_HD_26...

Page 29: ...3 JX2_HP_DP_12_GC_N 83 84 GND N A N A GND 85 86 JX2_HP_DP_15_P C5 A9 JX2_HP_DP_14_P 87 88 JX2_HP_DP_15_N B5 A8 JX2_HP_DP_14_N 89 90 GND N A N A GND 91 92 JX2_HP_DP_17_P H1 C8 JX2_HP_DP_16_P 93 94 JX2_HP_DP_17_N G1 B8 JX2_HP_DP_16_N 95 96 GND N A N A GND 97 98 JX2_HP_DP_19_P G7 A6 JX2_HP_DP_18_P 99 100 JX2_HP_DP_19_N F7 A5 JX2_HP_DP_18_N 101 102 GND N A N A GND 103 104 JX2_HP_DP_21_P G8 H6 JX2_HP_D...

Page 30: ... 15 16 GND N A N A GND 17 18 GTR_RX1_P H24 N A GND 19 20 GTR_RX1_N H25 K24 GTR_TX0_P 21 22 GND N A K25 GTR_TX0_N 23 24 GND N A N A GND 25 26 GTR_RX0_P M24 E22 GTR_REFCLK3_P 27 28 GTR_RX0_N M25 E23 GTR_REFCLK3_N 29 30 GND N A F22 H22 MGTRAVCC 31 32 GTR_REFCLK2_P G22 J22 GTR_REFCLK1_P 33 34 GTR_REFCLK2_N G23 J23 GTR_REFCLK1_N 35 36 MGTRAVTT A24 B22 D22 F22 H22 MGTRAVCC 37 38 GTR_REFCLK0_P L22 F22 H2...

Page 31: ...ZU3EG Bank Voltage Domain I O Usage JX1_HP_DP_ 00 23 _P N 64 VCCO_HP_64 Single Ended or Differential I O JX1_HP_DP_ 24 41 _P N 65 VCCO_HP_65 Single Ended or Differential I O JX1_HP_SE_ 00 03 64 VCCO_HP_64 Single Ended JX1_HP_SE_ 04 05 65 VCCO_HP_65 Single Ended JX2_HP_DP_ 00 23 _P N 66 VCCO_HP_66 Single Ended or Differential I O JX2_HP_DP_ 24 29 _P N 65 VCCO_HP_65 Single Ended or Differential I O ...

Page 32: ...ower to the PL VCCIO pins on the JX connectors until the SOM_PG_OUT signal becomes active 2 14 Configuration Modes The Zynq UltraScale MPSoC device uses a multi stage boot process that supports both non secure and secure boot The PS is the master of the boot and configuration process Upon reset the device PS MODE pins are read to determine the primary boot device to be used The UltraZed EG SOM all...

Page 33: ...ynq UltraScale MPSoC will not automatically reconfigure the PL as in standard FPGAs by toggling PROG Likewise it is not possible to hold off Zynq boot up with INIT_B as this is done with PS_POR_B If the application needs to reconfigure the PL the software design must do this or you can toggle the PS_POR_B to restart everything When PL configuration is complete a blue DONE LED will illuminate 2 14 ...

Page 34: ...VCCO_HP_65 and Bank 66 VCCO_HP_66 voltages are generated on the end user carrier card and connected to the UltraZed EG SOM via the Micro Headers The voltage at which these banks operate is up to the end user carrier card design as all I O that connect to these banks is exclusive to the Micro Headers no on board device is connected to these banks The diagram below shows a high level depiction of th...

Page 35: ...PSINTLP VCC_PSINTFP 0 85V VCC_PSINTFP VCC_PSINTFP_DDR VCC_PSPLL 1 2V VCC_PSPLL VCCO_PSDDR_504 1 2V VCCO_PSDDR_504 VCCINT_IO 0 85V VCCBRAM VCCINT_IO 3 3V 3 3V N A VCCINT 0 85V VCCINT VCC_PSDDR_PLL 1 8V VCC_PSDDR_PLL VIN 5V or 12V N A JX1 JX2 VCCO_HP_64 1 0V to 1 8V VCCO_64 Bank 64 JX1 VCCO_HP_65 1 0V to 1 8V VCCO_65 Bank 65 JX1 VCCO_HP_66 1 0V to 1 8V VCCO_66 Bank 66 JX2 VCCO_HD_26 1 2V to 3 3V VCC...

Page 36: ...or completing the power sequence These two supplies are the last regulators to be brought up The UltraZed EG SOM provides a power good signal to the end user carrier card to signal that the SOM power sequencing has completed and the end fuser carrier card is free to bring up the VCCO supplies This signal is called SOM_PG_OUT and is tied to JX2 Pin 41 SOM_PG_OUT on the Micro Headers serves to gate ...

Page 37: ... 1 5A PL Y N N VCCO_PSIO_501 1 8V to 3 3V 0 5A PS LP Y Y Y MGTRAVCC 0 85V 1 5A PS FP Y Y N MGTRAVTT 1 8V 1 0A PS FP Y Y N PS_VBATT 1 5V 0 5A N A Y Y Y Max Current Derived using Preliminary Xilinx Power Estimator Tools On Board Max Current Derived using Micro Header Pin Current Carrying Capacity Carrier Card 2 15 3 Power Supply Sequencing and Power Modes Sequencing for the power supplies follows th...

Page 38: ...BRAM VCCAUX VCCAUX_IO VCCO_HD_26 VCCO_HP_64 VCCO_HP_65 VCCO_HP_66 UltraZed EG SOM Implementation VCCINT VCCINT_IO VCCAUX VCCO_HD_26 VCCO_HP_64 VCCO_HP_65 VCCO_HP_66 Entering Exiting Power Domains To enter power down modes the reverse order of start up should be followed last supply to come up should be the first to be shut down etc The PL and PS FP domains can be powered down independently and eit...

Page 39: ...Version 1 0 Page 39 Figure 15 UltraZed Power On Sequence Figure 16 UltraZed Power Off Sequence ...

Page 40: ...ows at a minimum the PCB decoupling strategy as outlined in UG583 for the Zynq UltraScale MPSoC in the SFVA625 package NOTE These quantities are considered preliminary and subject to change because power and package modelling is still in progress at Xilinx A review of these requirements is required as this design moves from engineering silicon to production silicon Figure 18 PCB Decoupling Capacit...

Page 41: ...ated operating scenario NOTE When designing a custom UltraZed EG carrier board be sure to use XPE Xilinx Power Estimator to estimate the power needed by the Zynq UltraScale MPSoC device The designer will need this figure in sizing the input supply to the UltraZed EG SOM NOTE In addition to the XPE results for the Zynq UltraScale MPSoC the end user will need to add to their power estimate to compen...

Page 42: ...cally supplied by a battery This supply is typically used to maintain an encryption key in battery backed RAM for device secure boot The encryption key can alternatively be stored in eFuse which does not require a battery On the UltraZed EG SOM PS_VBATT is interfaced to the JX3 connector relying on the end user carrier card to properly implement the battery functionality To apply an external batte...

Page 43: ...the 5V conductor as pin 2 on the connector For reference the fan supplied with the UltraZed EG SOM mates with the fan header on the UltraZed IO Carrier Card Under most circumstances this 19 05mm Heatsink and Fan assembly should provide adequate relief across temperature but it cannot be guaranteed to support all environmental conditions due to lack of knowledge regarding end users thermal environm...

Page 44: ...I2C 2 24 25 TOTAL 50 The General Purpose I O assignments aren t specifically defined interfaces such as those that are defined in Table 32 The table below provides the MIO locations of the PS MIO general purpose pins and also MIO pins that support other functions Table 36 PS MIO General Purpose I O Peripheral Options Interface I O Required MIO QSPI FB CLK 1 6 MIO23_INT_N 1 23 General Purpose PS MI...

Page 45: ...VCCO_HP_64 ADJ Carrier Card Bank 65 VCCO_HP_65 ADJ Carrier Card Bank 66 VCCO_HP_66 ADJ Carrier Card PL I O Banks 26 64 65 and 66 are powered from the end user carrier card These bank supplies are designed to be independent on the UltraZed EG SOM Maximum flexibility is allowed to the designer for these banks as the voltage level and standards are left to the end user carrier card design The designe...

Page 46: ...Version 1 0 Page 46 4 Mechanical The UltraZed EG SOM measures 2 00 x 3 50 50 80 mm x 88 9 mm Figure 21 UltraZed EG SOM Top View Mechanical Dimensions ...

Page 47: ...tion using the smallest heatsink is 0 750 19 05 mm Figure 23 UltraZed EG SOM Fan and Heatsink Vertical Dimensions Note The above figure does not show the additional hardware required to attach the fan to the heatsink This additional hardware coincides with approximately 0 156 inches 3 96mm of additional height for the nut and screw The heatsink delivered with the UltraZed EG SOM has a height of 0 ...

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