Avnet UltraZed-EG, Hardware User'S Manual

Page: 3 / 47

Version 1.0 Page 3
Contents
1 Introduction ...........................................................................................................5
2 Functional Description ...........................................................................................7
2.1 Zynq Ult MPSoC ........................................................................................................ 7
2.2 Memory .................................................................................................................................... 7
2.2.1 DDR4 ................................................................................................................................... 7
2.2.2 Dual Parallel (x8) QSPI Flash .............................................................................................. 9
2.2.3 eMMC x8 Flash (Multi-Media Controller) ........................................................................... 10
2.2.4 SFVA625 Device Package Delay Compensation for Memory Interfaces ......................... 11
2.3 GTR Transceivers .................................................................................................................. 11
2.3.1 SFVA625 Device Package Delay Compensation for GTR Transceiver Interface ............. 12
2.4 USB 2.0 OTG ......................................................................................................................... 12
2.4.1 SFVA625 Device Package Delay Compensation for USB2.0 Interface ............................ 13
2.5 10/100/1000 Ethernet PHY .................................................................................................... 14
2.5.1 Ethernet PHY Strapping Resistors .................................................................................... 15
2.5.2 Ethernet PHY LEDs ........................................................................................................... 16
2.5.3 SFVA625 Device Package Delay Compensation for 10/100/1000 Ethernet Interface...... 16
2.6 I2C I/O Expander ................................................................................................................... 17
2.7 I2C Switch/Multiplexer ........................................................................................................... 18
2.7.1 End-User Carrier Card I2C Interface ................................................................................. 19
2.7.2 PMBUS Interface ............................................................................................................... 20
2.8 I2C EEPROM ......................................................................................................................... 21
2.9 PS General Purpose Interrupt ............................................................................................... 21
2.10 User I/O.................................................................................................................................. 21
2.10.1 PS MIO User Pins .............................................................................................................. 21
2.10.2 PL IO User Pins ................................................................................................................. 22
2.11 Clock Sources ........................................................................................................................ 22
2.12 Control Signal Sources .......................................................................................................... 23
2.12.1 Power-On Reset (PS_POR_N) and Carrier Card Reset (CC_RESET_OUT_N) .............. 23
2.12.2 PS_PROG_B, PS_DONE, PS_INIT_B, PUDC_B, POR_OVERRIDE, and ERROR ........ 23
2.12.3 Processor Subsystem Reset (PS_SRST_B) and SOM Reset (SOM_RESET_IN_N) ...... 24
2.13 Expansion Headers ............................................................................................................... 24
2.13.1 Micro Headers ................................................................................................................... 24
2.13.2 JX Connector Master Table ............................................................................................... 26
2.13.3 Powering the PL Banks (SOM_PG_OUT) ......................................................................... 32
2.14 Configuration Modes .............................................................................................................. 32
2.14.1 JTAG Connections ............................................................................................................. 33