ATtiny15L
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Internal Voltage Reference
ATtiny15L features an internal bandgap reference with a nominal voltage of 1.22V. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator. The 2.56V reference to the ADC is generated from the
internal bandgap reference.
Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The maximum start-up time is TBD.
To save power, the reference is not always turned on. The reference is on during the following situations:
1.
When the BOD is enabled (by programming the BODEN fuse).
2.
When the bandgap reference is connected to the Analog Comparator (by setting the AINBG bit in ACSR).
3.
When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the AINBG bit, the user must always allow the reference to start-up before
the output from the Analog Comparator is used. The bandgap reference uses typically 10 µA, and to reduce power con-
sumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off
before entering power-down mode.
Interrupt Handling
The ATtiny15L has two 8-bit Interrupt Mask control registers: GIMSK – General Interrupt Mask register and TIMSK –
Timer/Counter Interrupt Mask register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user soft-
ware can set the I-bit (one) to enable interrupts. The I-bit is set (one) when a Return from Interrupt instruction – RETI – is
executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hard-
ware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set
and remembered until the interrupt is enabled, or the flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt
flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is
present.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is 4-clock-cycles minimum. After the 4-clock-cycles the
program vector address for the actual interrupt handling routine is executed. During this 4-clock-cycle period, the Program
Counter (9 bits) is pushed onto the Stack. The vector is often a relative jump to the interrupt routine, and this jump takes 2
clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the
interrupt is served
.
If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased
by 4-clock-cycles.
A return from an interrupt handling routine takes 4-clock-cycles. During these 4-clock-cycles, the Program Counter (9 bits)
is popped back from the Stack. When AVR exits from an interrupt, it will always return to the main program and execute
one more instruction before any pending interrupt is served.
