Atmel AVR ATtiny15L Advance Information Download Page 68

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ATtiny15L

Ordering Information

Power Supply

Speed (MHz)

Ordering Code

Package

Operation Range

2.7 - 5.5V

1.6

ATtiny15L-1PC

ATtiny15L-1SC

8P3

8S2

Commercial

C to 70

ATtiny15L-1PI

ATtiny15L-1SI

8P3

8S2

Industrial

(-40

C to 85

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S2

8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)

Summary of Contents for AVR ATtiny15L

Page 1: ...ammable via SPI Port Enhanced Power on Reset Circuit Programmable Brown out Detection Circuit Internal Calibrated 1 6 MHz Tuneable Oscillator Internal 25 6 MHz Clock Generator for Timer Counter Extern...

Page 2: ...continue functioning The ADC Noise Reduction mode facilitates high accuracy ADC measurements by stopping the CPU while allowing the ADC to continue functioning The Power down mode saves the register c...

Page 3: ...R GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER COUNTER0 INSTRUCTION DECODER DATA DIR REG PORT B DATA REGISTER PORT B PROGRAMMING LOGIC TIMING AND CONTROL TIMER COUNTER1 MCU STATUS REGISTER STA...

Page 4: ...al variation 0 8 MHz 1 6 MHz of the internal oscillator a tuning capability is built in Through an eight bit control register OSCCAL the system clock rate can be tuned with less than 1 steps of the no...

Page 5: ...program memory is in system programmable Flash memory With the relative jump and relative call instructions the whole address space is directly accessed All AVR instructions have a single 16 bit word...

Page 6: ...ose working registers Within a single clock cycle ALU operations between registers in the register file are executed The ALU operations are divided into three main categories arithmetic logic and bit...

Page 7: ...gister d Rd Register Indirect Figure 5 Indirect Register Addressing The register accessed is the one pointed to by the Z register low byte R30 Register Direct Two Registers Rd and Rr Figure 6 Direct R...

Page 8: ...nd RCALL Figure 8 Relative Program Memory Addressing Program execution continues at address PC k 1 The relative address k is 2048 to 2047 Constant Addressing Using the LPM Instruction Figure 9 Code Me...

Page 9: ...ibed on page 25 specifying the EEPROM Address Register the EEPROM Data Register and the EEPROM Control Register Memory Access and Instruction Execution Timing This section describes the general access...

Page 10: ...Table 2 ATtiny15L I O Space Address Hex Name Function 3F SREG Status Register 3B GIMSK General Interrupt Mask Register 3A GIFR General Interrupt Flag Register 39 TIMSK Timer Counter Interrupt Mask Re...

Page 11: ...ment Overflow Flag The two s complement overflow flag V supports two s complement arithmetics See the Instruction Set Description for detailed information Bit 2 N Negative Flag The negative flag N ind...

Page 12: ...ler 007 rjmp ANA_COMP Analog Comparator handler 008 rjmp ADC ADC Conversion Handler 009 MAIN instr xxx Main program start Table 3 Reset and Interrupt Vectors Vector No Program Address Source Interrupt...

Page 13: ...d the program starts execution from address 000 The instruction placed in address 000 must be an RJMP relative jump instruction to the reset handling routine If the pro gram never enables an interrupt...

Page 14: ...ition Min Typ Max Units VPOT Power on Reset Threshold Voltage rising BOD disabled 1 0 1 4 1 8 V BOD enabled 1 7 2 2 2 7 V Power on Reset Threshold Voltage falling 1 BOD disabled 0 4 0 6 0 8 V BOD enab...

Page 15: ...hing the power on reset threshold volt age invokes a delay counter which determines the delay for which the device is kept in RESET after VCC rise The time out period of the delay counter can be defin...

Page 16: ...enabled BODEN programmed and VCC decreases below the trigger level the brown out reset is immediately activated When VCC increases above the trigger level the brown out reset is deactivated after a d...

Page 17: ...to the flag Bit 2 BORF Brown out Reset Flag This bit is set one if a brown out reset occurs The bit is reset zero by a power on reset or by writing a logic zero to the flag Bit 1 EXTRF External Reset...

Page 18: ...ars the corresponding flag that generated the interrupt Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position s to be cleared If an interrupt condition occurs...

Page 19: ...Res Reserved bits These bits are reserved bits in the ATtiny15L and always read as zero The General Interrupt Flag Register GIFR Bit 7 Res Reserved Bit This bit is a reserved bit in the ATtiny15L and...

Page 20: ...bit is a reserved bit in the ATtiny15L and always reads as zero Bit 6 OCF1A Output Compare Flag 1 A The OCF1A bit is set one when compare match occurs between Timer Counter1 and the data value in OCR...

Page 21: ...ple the external interrupt This implies that one external event might cause several interrupts The values on the pins are sampled before detecting edges If pin change interrupt is enabled pulses that...

Page 22: ...This will reduce power consumption in Idle mode ADC Noise Reduction Mode When the SM1 SM0 bits are 01 the SLEEP instruction forces the MCU into the ADC Noise Reduction mode stopping the CPU but allowi...

Page 23: ...l PLL for Fast Peripheral Clock Generation The internal PLL in ATtiny15L generates a clock frequency that is 16x multiplied from the RC oscillator system clock If the RC oscillator frequency is the no...

Page 24: ...r clock CK external source and stop can also be selected as clock sources Setting the PSR10 bit in SFIOR resets the prescaler This allows the user to operate with a predictable prescaler The Timer Cou...

Page 25: ...by hardware after the operation is performed Writing a zero to this bit will have no effect This bit will always be read as zero The 8 bit Timer Counter0 Figure 20 shows the block diagram for Timer Co...

Page 26: ...e prescaling source of Timer0 The Stop condition provides a Timer Enable Disable function The prescaled CK modes are scaled directly from the CK oscillator clock If the external pin modes are used for...

Page 27: ...iming functions with infrequent actions Figure 21 shows the block diagram for Timer Counter1 Figure 21 Timer Counter1 Block Diagram The two status flags overflow and compare match are found in the Tim...

Page 28: ...h with OCR1A register value If the control bit is cleared Timer Counter1 continues counting and is unaffected by a compare match Bit 6 PWM1 Pulse width Modulator Enable When set one this bit enables P...

Page 29: ...ata to be continuously compared with Timer Counter1 Actions on compare matches are specified in TCCR1 A compare match does only occur if Timer Counter1 counts to the OCR1A value A software write that...

Page 30: ...s the occurrence of odd length PWM pulses glitches in the event of an unsynchronized OCR1A write See Figure 22 for an example Figure 22 Effects of Unsynchronized OCR Latching During the time between t...

Page 31: ...d global interrupts are enabled This also applies to the Timer Output Compare A flag and interrupt The frequency of the PWM will be Timer Clock Frequency divided by OCR1B value 1 Bit 7 6 5 4 3 2 1 0 2...

Page 32: ...le This bit must be set one when the WDE bit is cleared Otherwise the watchdog will not be disabled Once set hardware will clear this bit to zero after four clock cycles Refer to the description of th...

Page 33: ...to prevent unintentional EEPROM writes a two state write procedure must be followed Refer to the description of the EEPROM Control Register for details on this When the EEPROM is read or written the...

Page 34: ...al 3 Write new EEPROM data to EEDR optional 4 Write a logical one to the EEMWE bit in EECR 5 Within four clock cycles after setting EEMWE write a logical one to EEWE Caution An interrupt between step...

Page 35: ...ltage matches the detection level If not an external low VCC Reset Protection circuit can be applied 2 Keep the AVR core in Power down Sleep mode during periods of low VCC This will prevent the CPU fr...

Page 36: ...is set one and the I bit in SREG is set one ACI is cleared by hardware when executing the corresponding interrupt handling vector Alternatively ACI is cleared by writing a logic one to the flag Bit 3...

Page 37: ...and four single ended voltage inputs constructed from the pins of Port B The dif ferential input PB3 PB4 is equipped with a programmable gain stage providing amplification step of 26 dB 20x on the di...

Page 38: ...ting of the MUX2 0 bits in ADMUX This amplified value then becomes the analog input to the ADC If single ended channels are used the gain amplifier is bypassed altogether If ADC2 is selected as both t...

Page 39: ...to the data regis ters is prohibited between reading of ADCH and ADCL the interrupt will trigger even if the result is lost Prescaling and Conversion Timing Figure 26 ADC Prescaler The successive appr...

Page 40: ...s high Using Free Running mode and an ADC clock frequency of 200 kHz gives the lowest conversion time 65 s equivalent to 15 kSPS For a summary of conver sion times see Table 17 Figure 27 ADC Timing Di...

Page 41: ...selected and the ADC conversion complete interrupt must be enabled ADEN 1 ADSC 0 ADFR 0 ADIE 1 2 Enter ADC Noise Reduction mode or Idle mode The ADC will start a conversion once the CPU has been halt...

Page 42: ...its 2 0 MUX2 MUX0 Analog Channel and Gain Selection Bits 2 0 The value of these bits selects which analog input is connected to the ADC In case of differential input PB3 PB4 gain selection is also mad...

Page 43: ...el after entering Free Running Mode may result in undefined operation from the ADC Bit 4 ADIF ADC Interrupt Flag This bit is set one when an ADC conversion completes and the data registers are updated...

Page 44: ...is ready to be read In Free Running mode the next conversion will start immediately when the interrupt triggers If ADMUX is changed after the interrupt triggers the next conversion has already starte...

Page 45: ...e Ended Conversion VREF 4V ADC clock 1 MHz 4 LSB Single Ended Conversion VREF 4V ADC clock 2 MHz 16 LSB Integral Non linearity VREF 2V 0 5 LSB Differential Non linearity VREF 2V 0 5 LSB Zero Error Off...

Page 46: ...and PB5 have alternative functions as inputs for the ADC If some Port B pins are configured as outputs it is essential that these do not switch when a conversion is in progress This might corrupt the...

Page 47: ...0 T0 PORT B Bit 2 In serial programming mode this pin serves as the serial clock input SCK In normal mode this pin can serve as the external interrupt0 input See the interrupt description for details...

Page 48: ...ult value is unprogrammed 1 Programming this fuse while in the Low voltage Serial programming mode will disable future in system downloading attempts CKSEL1 0 Fuses See Table 5 Reset Delay Selections...

Page 49: ...a into the ATtiny15L inside the user s system The Program and Data memory arrays in the ATtiny15L are programmed byte by byte in either programming modes For the EEPROM an auto erase cycle is provided...

Page 50: ...pin goes high 3 The EEPROM array is programmed one byte at a time by supplying first the address then the data byte The write instruction is self timed wait until the PB2 RDY BSY pin goes high 4 Any m...

Page 51: ...xxx_xx 0_0000_0000_00 0_0110_1100_00 o_oooo_ooox_xx Repeat Instr 1 and Instr 2 for each new address Read Flash High byte PB0 PB1 PB2 0_0000_0000_00 0_0111_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_...

Page 52: ...s programmed Read Signature Bytes PB0 PB1 PB2 0_0000_1000_00 0_0100_1100_00 x_xxxx_xxxx_xx 0_0000_00bb_00 0_0000_1100_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_0110_1000_00 x_xxxx_xxxx_xx 0_0000_0000_00 0_01...

Page 53: ...m and EEPROM arrays into FF The Program and EEPROM memory arrays have separate address spaces 0000 to 01FF for Program memory and 000 to 03F for EEPROM memory The device is clocked from the internal c...

Page 54: ...ime by supplying the address and data together with the appropriate Write instruction An EEPROM memory location is first automatically erased before new data is written Use Data Polling to detect when...

Page 55: ...ry at word address a b Write Program Memory 0100 H000 xxxx xxxa bbbb bbbb iiii iiii Write H high or low data i to Program memory at word address a b Read EEPROM Memory 1010 0000 xxxx xxxx xxbb bbbb oo...

Page 56: ...7V 4 0V 5 0V tWD_ERASE 6 ms 5 ms 4 ms Table 29 Minimum wait delay after writing a Flash or EEPROM location Symbol 2 7V 4 0V 5 0V tWD_PROG_EE 6 ms 5 ms 4 ms tWD_PROG_FL 3 ms 2 5 ms 2 ms Absolute Maximu...

Page 57: ...own is 1 5V Only with BOD disabled DC Characteristics Preliminary Data TA 40 C to 85 C VCC 2 7V to 5 5V Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage Except XTAL 0 5 0 3 VCC 1 V V...

Page 58: ...ge and frequency The current drawn from capacitive loaded pins may be estimated for one pin as CL VCC f where CL load capacitance VCC operating voltage and f average switching frequency of I O pin The...

Page 59: ...ffset Voltage vs Common Mode Voltage 0 2 4 6 8 10 12 14 16 18 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 ANALOG COMPARATOR OFFSET VOLTAGE vs V 5V cc COMMON MODE VOLTAGE Common Mode Voltage V Offset Voltage mV T...

Page 60: ...ities of I O ports are measured on one pin at a time 60 50 40 30 20 10 0 10 0 0 5 1 5 1 2 2 5 3 5 3 4 4 5 5 6 6 5 7 5 5 ANALOG COMPARATOR INPUT LEAKAGE CURRENT T 25 C A I nA ACLK V V IN V 6V CC 0 200...

Page 61: ...tor Current vs Input Voltage 0 20 40 60 80 100 120 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 PULL UP RESISTOR CURRENT vs INPUT VOLTAGE V 5V cc I A OP V V OP T 85 C A T 25 C A 0 5 10 15 20 25 30 0 0 5 1 1 5 2 2...

Page 62: ...rrent vs Output Voltage 0 10 20 30 40 50 60 70 0 0 5 1 1 5 2 2 5 3 V 5V cc I mA OL V V OL T 85 C A T 25 C A I O PIN SINK CURRENT vs OUTPUT VOLTAGE 0 2 4 6 8 10 12 14 16 18 20 0 0 5 1 1 5 2 2 5 3 3 5 4...

Page 63: ...I O Pin Source Current vs Output Voltage 0 5 10 15 20 25 0 0 5 1 1 5 2 I mA OL V V OL T 85 C A T 25 C A I O PIN SINK CURRENT vs OUTPUT VOLTAGE V 2 7V cc 0 1 2 3 4 5 6 0 0 5 1 1 5 2 2 5 3 I O PIN SOUR...

Page 64: ...gure 48 I O Pin Input Hysteresis vs VCC 0 0 5 1 1 5 2 2 5 2 7 4 0 5 0 Threshold Voltage V Vcc I O PIN INPUT THRESHOLD VOLTAGE vs Vcc T 25 C A 0 0 02 0 04 0 06 0 08 0 1 0 12 0 14 0 16 0 18 2 7 4 0 5 0...

Page 65: ...PSR1 PSR0 25 2B Reserved 2A Reserved 29 Reserved 28 Reserved 27 Reserved 26 Reserved 25 Reserved 24 Reserved 23 Reserved 22 Reserved 21 WDTCR WDTOE WDE WDP2 WDP1 WDP0 32 20 Reserved 1F Reserved 1E EEA...

Page 66: ...C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 2 or 3 None 1 2 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC...

Page 67: ...C Rd 0 Z C N V 1 ASR Rd Arithmetic Shift Right Rd n Rd n 1 n 0 6 Z C N V 1 SWAP Rd Swap Nibbles Rd 3 0 Rd 7 4 Rd 7 4 Rd 3 0 None 1 BSET s Flag Set SREG s 1 SREG s 1 BCLR s Flag Clear SREG s 0 SREG s 1...

Page 68: ...Operation Range 2 7 5 5V 1 6 ATtiny15L 1PC ATtiny15L 1SC 8P3 8S2 Commercial 0 C to 70 C ATtiny15L 1PI ATtiny15L 1SI 8P3 8S2 Industrial 40 C to 85 C Package Type 8P3 8 lead 0 300 Wide Plastic Dual Inli...

Page 69: ...325 8 26 300 7 62 0 15 REF 430 10 9 MAX 012 305 008 203 020 508 012 305 213 5 41 205 5 21 330 8 38 300 7 62 PIN 1 050 1 27 BSC 212 5 38 203 5 16 080 2 03 070 1 78 013 330 004 102 0 8 REF 010 254 007 1...

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