ATtiny15L
15
Power-on Reset
A power-on reset (POR) pulse is generated by an on-chip detection circuit. The detection level is nominally defined in Table
4. The POR is activated whenever V
CC
is below the detection level. The POR circuit can be used to trigger the start-up
reset, as well as detect a failure in supply voltage.
A power-on reset (POR) circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold volt-
age invokes a delay counter, which determines the delay, for which the device is kept in RESET after V
CC
rise. The time-
out period of the delay counter can be defined by the user through the CKSEL fuses. The different selections for the delay
period are presented in Table 5. The RESET signal is activated again, without any delay, when the Vcc decreases below
detection level.
Figure 13.
“MCU Start-up, RESET Tied to V
CC
Figure 14.
MCU Start-up, RESET Extended Externally
VCC
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
VCC
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
