ATtiny15L
5
ATtiny15L Architectural Overview
The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single-clock-cycle access
time. This means that during one single-clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock
cycle.
Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This pointer is called the Z-pointer, and
can address the register file, IO file, and the Flash program memory.
Figure 2.
The ATtiny15L AVR RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single-register
operations are also executed in the ALU. Figure 2 shows the ATtiny15L AVR RISC microcontroller architecture. The AVR
uses a Harvard architecture concept with separate memories and buses for program and data memories. The program
memory is accessed with a two-stage pipelining. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is
in-system programmable Flash memory.
With the relative jump and relative call instructions, the whole address space is directly accessed. All AVR instructions have
a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a
3 level deep hardware stack dedicated for subroutines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, and
other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-
gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.
512 x 16
Program
FLASH
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Direct Addressing
Status
and Test
Control
Registrers
Interrupt
Unit
2 x 8-bit
Timer/Counter
Watchdog
Timer
Analog
Comparator
I/O Lines
Data Bus 8-bit
SPI Unit
ADC
64 x 8
EEPROM
