ATtiny15L
17
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse,
the delay timer starts counting the Time-out period t
TOUT
. Refer to page 32 for details on operation of the Watchdog Timer.
Figure 17.
Watchdog Reset During Operation
MCU Status Register – MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset.
•
Bit 7..4 - Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and always read as zero.
•
Bit 3 - WDRF: Watchdog Reset Flag
This bit is set (one) if a watchdog reset occurs. The bit is reset (zero) by a power-on reset, or by writing a logic zero to the
flag.
•
Bit 2 - BORF: Brown-out Reset Flag
This bit is set (one) if a brown-out reset occurs. The bit is reset (zero) by a power-on reset, or by writing a logic zero to the
flag.
•
Bit 1 - EXTRF: External Reset Flag
This bit is set (one) if a external reset occurs. The bit is reset (zero) by a power-on reset, or by writing a logic zero to the
flag.
•
Bit 0 - PORF: Power-on Reset Flag
This bit is set (one) if a power-on reset occurs. The bit is reset (zero) by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as
possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by
examining the reset flags.
Bit
7
6
5
4
3
2
1
0
$34
-
-
-
-
WDRF
BORF
EXTRF
PORF
MCUSR
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
See bit description
1 CK Cycle
