22
2.14 SYSTEM ERRORS
The 68000 has a feature called exception processing, which takes place when an
interrupt or bus error is indicated by external logic, or when the CPU detects an error
internally, or when certain types of instructions are executed. An exception will cause
the CPU to fetch a vector (address to a routine) from RAM and start processing at
the routine pointed to by the vector. Exception vectors are initialized by the operating
system. Those exceptions which do not have legitimate occurrences (interrupts
being legitimate) have vectors pointing to a general purpose routine which will
display some number of bombs showing on the screen. The number of bombs
equals the number of exceptions which occurred. System errors may or may not be
recoverable. Errors in loading files from disk may cause the system to crash,
necessitating a reset. Verify the diskette and disk drive before attempting to repair
the computer.
2.14.1 Number of Bombs and Meaning
2:
BUS ERROR.
GSTMCU asserted bus error.
3:
ADDRESS ERROR_
Processor attempted to access word or long word
sized data on an odd address.
4:
ILLEGAL INSTRUCTION.
Processor fetched an instruction from ROM
or RAM which was not a legal instruction.
5:
ZERO
DIVIDE.
Processor was asked to perform a division by zero.
6:
CHK INSTRUCTION.
This is a legal instruction, if software uses this, it
must install a handler.
7:
TRAPV INSTRUCTION.
See Chk instruction.
8:
PRIVILEGE VIOLATION.
CPU was in user mode, tried to execute a
68000 instruction that can only be performed in supervisor mode.
9:
TRACE.
If trace bit is set in the status register, the CPU will execute
this exception after every instruction. Used to debug software.
10
:
LINE 1010 EMULATOR.
CPU read an instruction which has '1010' as
its most significant nibble. Used by TOS for low level graphics software
routines.
11:
LINE 1111 EMULATOR.
CPU read an instruction which has ' 1111' as
its most significant nibble. Used internally in earlier versions of TOS,
but reserved on STE.
12:
12–23 Unassigned
, should be no occurrence.
24:
SPURIOUS INTERRUPT.
Bus error during interrupt processing.
25–31: AUTOVECTOR INTERRUPT.
Numbers 4 and 2 are used,
others should have no occurrence.
32–63: TRAP INSTRUCTION.
CPU read instruction which is used to generate
a software exception (such as the entry to GEMDOS, VDI, or AES).
64–79:
MFP interrupts.
80–127:
Reserved for Atari use.
128–255:
Unused.
Summary of Contents for 1040STE
Page 1: ......
Page 2: ...II Atari STe 520 1040 Computer Field Service Manual Part Number C302481 001 Rev A August 1991...
Page 23: ...18 Figure 2 8 STE Functional Block Diagram...
Page 24: ...19 Figure 2 9 STE DMA Block Diagram...
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Page 53: ...48 Figure 6 1 STE Diagnostic Flow Chart...
Page 54: ...49 Figure 6 2 STE Diagnostic Flow Chart...
Page 55: ...50 Figure 6 3 STE Diagnostic Flow Chart...
Page 56: ...51 Figure 6 4 STE Diagnostic Flow Chart...
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Page 81: ...ATARI STE TEST FIXTURE TO COMPUTER CONNECTION...