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MEMORY CONTROLLER
Atari proprietary chip which handles all RAM accesses.
See Theory of Operation, Main System and Video Subsystem for details.
MIDI
Musical Instrument Digital Interface. An electrical standard by which electronic
instruments communicate. Also, the logical system for such communication. In the
STE. consists of a 6850 communication chip, driver and receiver chips (74LS04,
74LS05, and PC-900 optoisolator), and an MFP interrupt channel.
MFP
Multi-Function Peripheral, aka 68901. Interrupt control, timers, and USART for
RS232 communication. See Theory of Operation, Main System.
MODULATOR
Device which modulates a composite video signal, combined with
audio. onto an RF carrier for output to a television.
PHASE LOCKED LOOP
Circuit which locks the horizontal sync signal onto the color
burst reference frequency for accurate color on the T.V. Without this circuit, colors on
the T. V. become unstable, flickering or shifting about on the screen.
PSG
Programmable Sound Generator, also YM2149. Yamaha version of General
Instruments AY-3-8910. Has two 8 bit I/O ports and three sound channels. Used in
parallel port and audio.
RS232C
Electrical standard for serial digital communication. Also the physical and
logical device which performs communication using this standard. In the STE
computers, consists of the MFP, PSG, 1488, and 1489 chips.
SUPERVISOR MODE
State of the CPU in which it is allowed to access all hardware
and RAM locations, and perform some privileged instructions. Determined by the
state of a bit in the Status Register.
USER MODE
State of the CPU in which certain instructions and areas in the
memory map are disallowed (resulting in a privilege violation exception if attempted).
See also SUPERVISOR MODE.
VSYNC
Signal used for vertical synchronization of CRT display device. Occurs at 70
Hz (monochrome), or 50 or 60 HZ color.
YM2149
See PSG
Summary of Contents for 1040STE
Page 1: ......
Page 2: ...II Atari STe 520 1040 Computer Field Service Manual Part Number C302481 001 Rev A August 1991...
Page 23: ...18 Figure 2 8 STE Functional Block Diagram...
Page 24: ...19 Figure 2 9 STE DMA Block Diagram...
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Page 53: ...48 Figure 6 1 STE Diagnostic Flow Chart...
Page 54: ...49 Figure 6 2 STE Diagnostic Flow Chart...
Page 55: ...50 Figure 6 3 STE Diagnostic Flow Chart...
Page 56: ...51 Figure 6 4 STE Diagnostic Flow Chart...
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Page 81: ...ATARI STE TEST FIXTURE TO COMPUTER CONNECTION...