6
Controller, to synchronize data transfer. It arbitrates the bus during DMA
transfers to
prevent CPU and DMA devices from interfering with each other (see
DMA
below).
ILLEGAL CONDITION DETECTION
GSTMCU asserts Bus Error (BERR) if certain
conditions are violated, such as writing to ROM, writing to system memory when the
processor is in user mode, or if no device responds within 64 cycles of the 8 MHz
clock (8Ns). For example, if the CPU tries to read from beyond the end of memory,
the Memory Controller will not assert DTACK, resulting in a bus error which will
terminate the memory cycle.
MEMORY CONTROLLER
takes addresses from the address bus and converts to
Row Address Strobe (RAS) and Column Address Strobe (CAS). All
RAM
accesses
are controlled by this Atari proprietary chip, which is programmable for up to 4
Megabytes of memory. The Operating System determines how much memory is
present and configures the Memory Controller at power–up. The Memory Controller
refreshes the dynamic RAMs, loads the Video Shifter with display data, and gives or
receives data during direct memory access (DMA). The Memory Controller produces
all of the addresses for video, sound, and DMA on the multiplexed address bus.
These addresses never appear on the system address bus.
CHIP SELECTS
Decodes addresses for RAM and ROM and asserts output signals
to enable these devices.
2.6 MAIN MEMORY
Main memory consists of 256 kbytes of ROM and one or two banks (512 kbyte each)
of dynamic RAM. In addition, the cartridge slot allows access to 128 kbytes of ROM.
All memory is directly addressable. The components of the memory system are:
ROM, RAM, GSTMCU and shifter. The Operating System resides mostly in ROM,
with optional segments loaded from disk into RAM.
Each bank of RAM in the STE is made up of a pair of 8–bit wide SIMMs to create the
16–bit wide system memory bus. All of the SIMMs in the system must be the same
size. It is not possible to mix 256 kbit SIMMs and 1 Mbit SIMMs in the same system.
All of the SIMMs used should have the same access time, which can be no greater
than 150 ns.
It is possible to use 9–bit wide SIMMs, with the hardware simply ignoring the ninth
bit.
RAM MEMORY MAP:
000008–000800 System Memory (privileged access)
000800–07FFFF Low Bank
080000–0FFFFF High Bank (1040 only)
Note:
The first 8 bytes of ROM are mapped into addresses 0–7. These are reset
vectors which the 68000 uses on start–up.
The Operating System is located in two 128K x 8 ROM chips.
ROM MEMORY MAP.
E00000–E3FFFF
Summary of Contents for 1040STE
Page 1: ......
Page 2: ...II Atari STe 520 1040 Computer Field Service Manual Part Number C302481 001 Rev A August 1991...
Page 23: ...18 Figure 2 8 STE Functional Block Diagram...
Page 24: ...19 Figure 2 9 STE DMA Block Diagram...
Page 28: ...23...
Page 53: ...48 Figure 6 1 STE Diagnostic Flow Chart...
Page 54: ...49 Figure 6 2 STE Diagnostic Flow Chart...
Page 55: ...50 Figure 6 3 STE Diagnostic Flow Chart...
Page 56: ...51 Figure 6 4 STE Diagnostic Flow Chart...
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Page 81: ...ATARI STE TEST FIXTURE TO COMPUTER CONNECTION...