Atari 1040STE, Field Service Manual

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2. 7 DIRECT MEMORY ACCESS
A single direct memory access (DMA) channel is provided that is shared between
the internal floppy disk controller and external devices connected to the ACSI port.
Data can be transferred at up to 10 Megabits/sec (1.25 Megabytes/sec) across the
8–bit wide ACSI port.
For DMA to take place, the memory controller is programmed with the starting
address at the RAM buffer. The DMA controller is set up to select the source and the
number of 512 byte blocks to transfer, and then the FDC or external peripheral is
given the command to send or receive data. The entire block of data is then
transferred to or from memory
without intervention by the CPU. The FDC or peripheral generally asserts its interrupt
line to signal the completion of the transfer (and the availability of status information).
To access registers in the FDC or ACSI bus peripherals, the 68000 talks through the
DMA chip. The state of two address lines that are generated by the DMAC is set by
writing to the DMA control register. Then a 68000 read or write cycle causes the
corresponding cycle on the peripheral side of the DMAC.
2.8 MULTI–FUNCTION PERlPHERAL CONTROL
2.8.1 Interrupt Control
The 68901 MFP can generate up to 16 interrupts, 8 internally and 8 from external
sources. Each interrupt can be masked off or disabled by programming the MFP.
The 8 inputs are also directly readable by the CPU. When the MFP receives an
interrupt internally, if the interrupt is enabled, MFPINT will be driven low. When the
CPU is ready to respond, it signals interrupt acknowledge (FC2–FC0 high, A3–A1=6,
and R/W low) and GSTMCU will assert the MFPs IACK signal (interrupt
acknowledge). The MFP will assert DTACK and put a vector number on the data
bus, which the CPU will read and use to calculate the address of the interrupt
routine.
The interrupts controlled by the MFP are: monochrome monitor detect (MONOMON),
RS232 (including CTS, DCD, RI), disk (FDINT and HDINT), parallel port BUSY,
display enable (DE, equals the active part of a display line), 6850 IRQs for keyboard
and MIDI data, and MFP timers.
Not all I/O operations use interrupts. The CPU can also poll the MFP while waiting
for an operation to complete or to check the current status.
2.8.2 MFP Counter/Timers
The MFP clock runs at 2.4576 MHz. The MFP contains four timers:
Timer A Reserved for application software used in the original ST. In the STE, its
external event input is used to count DMA sound subsystem cycles.