27
3.5.1 Power–Up Initialization Errors
I1
Error in RAM or Data Bus. (Test walks 1 or 0 across data bus.)
I2
RAM Disturbance Error. (Writing to one location alters data in another
location.)
I3
RAM Addressing Error. (Test shows bad RAM cell or incorrect address code.)
I4
Memory Configuration Error. (Problem with Memory Controller or RAM.)
I5
RAM Sizing Error. (Incorrect amount of good RAM found.)
I6
Checking Exception Handling. (This message is always printed on power–up
initialization. If the system can fetch the vector from RAM and execute the
handling routine, the message will be erased later.)
I7
Bus Error Not Service. (If the GSTMCU does not assert the Bus Error signal,
this error will occur.)
T0
MFP Timer Error. (One or more of the four timers in the MFP did not generate
an interrupt.)
T1
Vertical Svnc. (GSTMCU is not generating vertical sync in the required time
period.)
T2
Horizontal Sync. (GSTMCU is not generating horizontal sync in the required
time period.)
T3
Display Enable. (GSTMCU is not generating DE output or the MFP is not
generating an interrupt.)
T4
Video Counter Error. (The Memory Controller is not generating the correct
address for the display. This will result in a broken–up display in some or all
display modes.)
T5
PSG Bus Error. The PSG chip is defective. (Replace chip.)
T6
1772 Bus Error. The 1772 chip is defective. (Replace chip.)
K0
Stuck Kev. A key closure was detected while the keyboard self test was
executing.
K1
Keyboard Not Responding. A command was sent to the keyboard processor
and no status was returned within the allowed time. Verify that the keyboard is
connected to the STE. Verify that Pin 4 of J202 is +5 VDC. Verify that Pin 3 of
U201 is 500 KHz ±50 KHz. Replace the keyboard, 0201. 8210. 8209.
K2
Keyboard Status Error. The self test command was sent to the keyboard, on
completion of the test, the keyboard sent an error status. Replace the
keyboard.
Summary of Contents for 1040STE
Page 1: ......
Page 2: ...II Atari STe 520 1040 Computer Field Service Manual Part Number C302481 001 Rev A August 1991...
Page 23: ...18 Figure 2 8 STE Functional Block Diagram...
Page 24: ...19 Figure 2 9 STE DMA Block Diagram...
Page 28: ...23...
Page 53: ...48 Figure 6 1 STE Diagnostic Flow Chart...
Page 54: ...49 Figure 6 2 STE Diagnostic Flow Chart...
Page 55: ...50 Figure 6 3 STE Diagnostic Flow Chart...
Page 56: ...51 Figure 6 4 STE Diagnostic Flow Chart...
Page 72: ......
Page 73: ......
Page 74: ......
Page 75: ......
Page 76: ......
Page 77: ......
Page 78: ......
Page 79: ......
Page 80: ......
Page 81: ...ATARI STE TEST FIXTURE TO COMPUTER CONNECTION...