Artesyn ATCA-7360, Installation And Use Manual

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Maps and Registers
ATCA-7360 Installation and Use (6806800J07S )
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6.3.4 UART1 and UART2 Register Map
The LPC IO Base addresses BASE1 for UART1 and BASE2 for UART2 are set up during Super IO
configuration. See
Super IO Configuration Registers on page 159 .
6.3.4.1 UART Register Overview
Table 6-26 on page 165 shows the registers and their addresses as offsets of a base address for
one of the two UARTs.
An Interrupt is activated by enabling this device (offset 0x30), setting this register to a non-
zero value and setting any combination of bits 0-4 in the corresponding UART IER and the
occurrence of the corresponding UART event (that is Modem Status Change, Receiver Line
Error Condition, Transmit Data Request, Receiver Data Available or Receiver Time Out) and
setting the OUT2 bit in the MCR.
Table 6-23 Logical Device 0x74 Reserved Register
Index Address: 0x74
Bit Description Default Access
7:0 Reserved 0x04 LPC: r
Table 6-24 Logical Device 0x75 Reserved Register
Index Address: 0x75
Bit Description Default Access
7:0 Reserved 0x04 LPC: r
Table 6-25 Logical Device 0xF0 Reserved Register
Index Address: 0xF0
Bit Description Default Access
7:0 Reserved 0x04 LPC: r