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ATCA-7490 Installation and Use (6806800U11F)

Contents

6

Contents

Contents

5.1.14.3 BIOS IPMC Watchdog Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.1.14.4 BIOS Push Button Enable Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.1.14.5 OS Reset Source Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.1.14.6 OS IPMC Watchdog Timeout Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.1.14.7 IPMC Watchdog Timeout Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.1.14.8 IPMC Reset Source Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.1.14.9 IPMC Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.1.14.10DIMM ADR Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.1.14.11DIMM ADR Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.1.14.12Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

5.1.15 CPU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.1.16 S-States Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.1.17 NMI Control Status Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

5.1.17.1 NMI Generation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.1.17.2 NMI Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

5.1.18 Interrupt Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

5.1.18.1 Internal Interrupt Status Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.1.18.2 Telecom Interrupt Status Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.1.18.3 Telecom Interrupt Control Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.1.18.4 RTM Interrupt Status Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.1.18.5 External Interrupt Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.1.18.6 Interrupt Mask and Map Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

5.1.19 PCI Express Hot Plug I2C IO Expander Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

5.1.19.1 CPU0 Hot Plug I2C IO Expander Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.1.19.2 CPU1 Hot Plug I2C IO Expander Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.1.19.3 Hot-Plug Virtual Pin Port Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.1.19.4 PCA9555 Internal Register access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

5.1.20 Flash Status and Selection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.1.21 PCH Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.1.22 RTM SPI Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.1.23 Update Channel Equalization Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.1.24 RTM USB Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.1.25 LED Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
5.1.26 Spare Signals Status Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
5.1.27 CPU Presence Detection Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
5.1.28 CPU Error Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Summary of Contents for ATCA-7490

Page 1: ...ATCA 7490 Installation and Use P N 6806800U11F December 2018 ...

Page 2: ...onal use or referenced in another document as a URL to an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Artesyn It is possible that this publication may contain reference to or information about Artesyn products machines and programs programming or services that are not available in you...

Page 3: ...e Blade 45 2 2 Environmental and Power Requirements 46 2 2 1 Environmental Requirements 46 2 2 2 Power Requirements 50 2 3 Blade Layout 52 2 4 Switch Settings 53 2 5 Installing the Blade Accessories 55 2 5 1 DIMM Memory Modules 55 2 5 2 SSD Carrier and MO297 SSD Modules 58 2 6 Installing and Removing the Blade 60 2 6 1 Installing the Blade 61 2 6 2 Removing the Blade 64 3 Controls Indicators and C...

Page 4: ...r Features 92 4 4 2 Intel i350 Quad GB Ethernet Controller 93 4 4 3 Firmware Flashes 93 4 5 ATCA Fabric IF Ethernet 93 4 6 Storage Controller 94 4 6 1 ATCA Update Channels 94 4 7 MO297 SlimSATA Embedded Solid State Disc SSD Carrier Riser Card 96 4 8 Heat Sink 96 4 9 BIOS 96 4 10 IPMC 96 4 10 1 I2C Bus 97 4 10 2 FRU Data serial IDROM 98 4 10 3 System Event Log EEPROM 99 4 11 Serial Redirection 99 4...

Page 5: ...LAB 0 118 5 1 4 3 Programmable Baud Rate Generator 131 5 1 5 FPGA Register Mapping 133 5 1 5 1 LPC I O Register Map 133 5 1 5 2 IPMC I2C Register Map 133 5 1 6 Module Identification Register 137 5 1 7 Version Register 137 5 1 8 Serial Redirection Control Register 137 5 1 9 Serial over LAN SOL Control Register 138 5 1 10 Serial Line Routing Register 139 5 1 11 IPMC Power Level Register 140 5 1 12 I...

Page 6: ...sters 161 5 1 18 1 Internal Interrupt Status Register 162 5 1 18 2 Telecom Interrupt Status Register 162 5 1 18 3 Telecom Interrupt Control Register 163 5 1 18 4 RTM Interrupt Status Register 163 5 1 18 5 External Interrupt Status Register 163 5 1 18 6 Interrupt Mask and Map Registers 164 5 1 19 PCI Express Hot Plug I2C IO Expander Registers 166 5 1 19 1 CPU0 Hot Plug I2C IO Expander Registers 166...

Page 7: ...3 Boot Support 187 6 3 1 Boot Mode 187 6 3 2 Boot Type 187 6 3 3 Supported Boot Devices 188 6 3 4 Selecting the Boot Device 188 6 3 5 By Boot Menu 190 6 4 SATA RAID Configuration 191 6 4 1 RAID Features 191 6 4 2 RAID Configuration 192 6 4 2 1 Enabling RAID mode in BIOS 192 6 4 2 2 RAID configuration for Legacy Boot Type 192 6 4 2 3 RAID configuration for UEFI Boot Type 194 6 5 iSCSI Boot 197 6 6 ...

Page 8: ...I Commands 259 8 1 Standard IPMI Commands 259 8 1 1 Global IPMI Commands 259 8 1 2 System Interface Commands 259 8 1 3 Watchdog Commands 260 8 1 4 SEL Device Commands 261 8 1 5 FRU Inventory Commands 261 8 1 6 Sensor Device Commands 262 8 1 7 Chassis Device Commands 263 8 1 7 1 System Boot Options Commands 263 8 1 8 LAN Device Commands 279 8 2 PICMG 3 0 Commands 279 8 3 Artesyn Specific Commands 2...

Page 9: ...ad Control Command 302 8 4 14 Disable Payload Control Command 302 8 4 15 Hang IPMC Command 303 8 4 16 Graceful Reset Command 303 8 4 17 Get Payload Shutdown Time Out Command 304 8 4 18 Set Payload Shutdown Time Out Command 305 8 4 19 Get Module State Command 305 8 4 20 Enable Module Site Command 307 8 4 21 Disable Module Site Command 307 8 4 22 Reset Carrier SDR Repository Command 308 9 IPMI Featu...

Page 10: ...10 Payload Power Failure Cause Sensor 341 9 4 POST 341 9 5 Ejector Handle De Bounce 342 9 6 FRU Inventory 342 9 6 1 MAC Address FRU OEM Records 343 9 7 Reset and Power Domain 345 9 8 Power Configuration 345 9 9 BIOS Boot Configuration Parameters 346 9 10 Asynchronous Event Notification 347 9 11 Serial Line Selection 347 9 12 BIOS Boot Bank Selection 348 9 12 1 Boot Bank Sensor 348 9 12 2 Fail Safe...

Page 11: ... Memory Statement 361 B 1 1 SPI Flash Processor 362 B 1 2 SPI Flash IPMC 364 B 1 3 USER Parameters 365 B 1 4 FPGA Configuration Flash 366 B 1 5 IPMC I2C EEPROM 367 C Related Documentation 369 C 1 Artesyn Embedded Technologies Embedded Computing Documentation 369 C 2 Manufacturers Documents 370 C 3 Related Specifications 370 ...

Page 12: ...ATCA 7490 Installation and Use 6806800U11F Contents 12 Contents Contents ...

Page 13: ... 94 Table 4 2 IPMI I2C Bus Address Map private I2C bus 97 Table 4 3 Faceplate Serial Interfaces 101 Table 4 4 IPMC Debug Console Destination Selection 101 Table 4 5 SMBus Interface 103 Table 4 6 SMBus Address Map 104 Table 5 1 Register Default 107 Table 5 2 Register Access Type 107 Table 5 3 LPC I O Register Map Overview 108 Table 5 4 IPMC I2C Register Map 109 Table 5 5 POST Code Register 109 Tabl...

Page 14: ...ble 5 29 Interrupt Identification Register Decode 121 Table 5 30 FIFO Control Register FCR 122 Table 5 31 Line Control Register LCR 123 Table 5 32 Modem Control Register MCR 125 Table 5 33 Line Status Register LSR 127 Table 5 34 Modem Status Register MSR 130 Table 5 35 Scratch Register SCR 131 Table 5 36 Divisor Latch LSB Register DLL if DLAB 1 132 Table 5 37 Divisor Latch MSB Register DLM if DLAB...

Page 15: ...IMM ADR Feature Configuration Register 157 Table 5 67 DIMM ADR Status Register 158 Table 5 68 Reset Control Register 158 Table 5 69 CPU Control Register 159 Table 5 70 S States Control Register 160 Table 5 71 NMI Generation Register 161 Table 5 72 NMI Interrupt Status Register 161 Table 5 73 Internal Interrupt Status Register 162 Table 5 74 Telecom Interrupt Status Register 162 Table 5 75 Telecom ...

Page 16: ...79 Table 5 102 Telecom Clock Monitor Lower Limit Register 179 Table 5 103 Telecom Clock Monitor Upper Limit Register 180 Table 5 104 BIOS Version Register 1 180 Table 5 105 BIOS Version Register 2 180 Table 5 106 BIOS Version Register 3 180 Table 5 107 IPMC BIOS Communication Register 1 181 Table 5 108 IPMC BIOS Communication Register 2 181 Table 5 109 IPMC BIOS Communication Register 3 181 Table ...

Page 17: ...mands 261 Table 8 6 Supported Sensor Device Commands 262 Table 8 7 Supported Chassis Device Commands 263 Table 8 8 Configurable System Boot Option Parameters 263 Table 8 9 System Boot Options Parameter 96 264 Table 8 10 System Boot Options Parameter 98 265 Table 8 11 System Boot Options Parameter 100 Data Format 267 Table 8 12 System Boot Options Parameter 100 SET Command Usage 267 Table 8 13 Syst...

Page 18: ...e Out Command Description 300 Table 8 40 Set Payload Communication Time Out Command Description 301 Table 8 41 Enable Payload Control Command Description 302 Table 8 42 Disable Payload Control Command Description 302 Table 8 43 Hang IPMC Command Description 303 Table 8 44 Graceful Reset Command Description 303 Table 8 45 Get Payload Shutdown Time Out Command Description 304 Table 8 46 Set Payload ...

Page 19: ...tion Depending on the Product Version 345 Table 9 11 IPMC Boot Parameter storage format 346 Table B 1 ATCA 7490 Nonvolatile Memory 361 Table C 1 Artesyn Embedded Technologies Embedded Computing Publications 369 Table C 2 Manufacturer s Documents 370 Table C 3 Related Specifications 370 ...

Page 20: ...ATCA 7490 Installation and Use 6806800U11F 20 List of Tables ...

Page 21: ...A to D 80 Figure 3 13 P22 Backplane Connector Pinout Rows E to H 81 Figure 3 14 P23 Backplane Connector Pinout Rows A to D 81 Figure 3 15 P23 Backplane Connector Pinout Rows E to H 82 Figure 3 16 P30 Backplane Connector Pinout Rows A to D 83 Figure 3 17 P30 Backplane Connector Pinout Rows E to H 83 Figure 3 18 P31 Backplane Connector Pinout Rows A to D 84 Figure 3 19 P31 Backplane Connector Pinout...

Page 22: ...7 Figure 6 20 Memory Configuration 219 Figure 6 21 Memory RAS Configuration 220 Figure 6 22 Console Redirection 222 Figure 6 23 APEI Configuration 223 Figure 6 24 BIOS Event Log Configuration 225 Figure 6 25 Event Log Viewer 226 Figure 6 26 Memory Event Log Viewer 227 Figure 6 27 IPMI Configuration 228 Figure 6 28 Security 230 Figure 6 29 Boot 231 Figure 6 30 EFI Boot Order 233 Figure 6 31 Legacy ...

Page 23: ...d ordering information of the blade Hardware Preparation and Installation on page 45 outlines the installation requirements hardware accessories switch settings installation and removal procedures Controls Indicators and Connectors on page 67 describes external interfaces of the blade This includes connectors and LEDs BIOS on page 183 describes the features and setup of BIOS Functional Description...

Page 24: ...bbreviations This document uses the following abbreviations Abbreviation Definition ADR Asynchronous DRAM Refresh APIC Advanced Programmable Interrupt Controller ASW Active Sleep Well ATA Advanced Technology Attachment ATCA Advanced Telecommunications Computing Architecture BIOS Basic Input Output System DDR Double Data Rate DIMM Dual Inline Memory Module DMA Direct Memory Access DMI Direct Media ...

Page 25: ...cess Control NEBS Network Equipment Building System NVRAM Nonvolatile Random Access Memory OEM Original Equipment Manufacturer OOS Out Of Service PCB Printed Circuit Board PCH Platform Controller Hub PCI Peripheral Component Interconnect PCIe PCI Express PCU Processor Power Control Unit PEM Power Entry Module PICMG PCI Industrial Computer Manufacturers Group PIM Power Input Module PMC PCI Mezzanin...

Page 26: ...Peripheral Interface SSC Spread Spectrum Clocking VLP Very Low Profile Abbreviation Definition Notation Description 0x00000000 Typical notation for hexadecimal numbers digits are 0 through F for example used for addresses and offsets 0b0000 Same for binary numbers digits are 0 and 1 bold Used to emphasize a word Screen Usedforon screenoutputandcoderelatedelements or commands in body text Courier B...

Page 27: ...and that is not necessary at the time being Ranges for example 0 4 means one of the integers 0 1 2 3 and 4 used in registers Logical OR Indicates a hazardous situation which if not avoided could result in death or serious injury Indicates a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message No danger encountered Pay attention to impo...

Page 28: ...tures on page 39 6806800U11E May 2017 Updated the section Advanced on page 205 6806800U11D January 2017 Updated the section Features on page 39 Table 1 3 on page 43 and Table 2 3 on page 51 6806800U11C September 2016 Updated Chapter 6 BIOS on page 183 6806800U11B August 2016 Updated DIP Switch setting in section BIOS POST Codes on page 243 and default value of SW2 4 in Switch SW2 Settings on page ...

Page 29: ...telecommunication industry and industrial control Only personnel trained by Artesyn or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment...

Page 30: ...e considered as debug maintenance ports During normal operation no cables must be connected to these ports Cables attached to these ports during maintenance must not exceed a length of 3m Installation Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or electronic components make sure that you...

Page 31: ...e Blade surface High humidity and condensation on the blade surface causes short circuits Do not operate the blade outside the specified environmental limits Make sure the blade is completely dry and there is no moisture on any surface before applying power Blade Overheating and Blade Damage Operating the blade without forced air cooling may lead to blade overheating and thus blade damage When ope...

Page 32: ...d changed before blade installation Blade Damage Setting resetting the switches during operation can cause blade damage Therefore check and change switch settings before you install the blade Battery Blade Damage Incorrect battery installation may result in hazardous explosion and blade damage Therefore always use the same type of Lithium battery as is installed and make sure the battery is instal...

Page 33: ...ötigen sollten wenden Sie sich bitte an die für Sie zuständige Geschäftsstelle von Artesyn Das System erfüllt die für die Industrie geforderten Sicherheitsvorschriften und darf ausschließlich für Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden Einbau Wartung und Betrieb dürfen nur von durch Artesyn ausgebildetem oder im Bereich Elektroni...

Page 34: ... Fall kann vom Betreiber verlangt werden angemessene Maßnahmen durchzuführen Die nachfolgend aufgeführten Schnittstellen sind Wartungsschnittstellen COM USB1 USB2 Während des Normalbetriebs darf an diesen Schnittstellen kein Kabel angeschlossen sein Im Wartungsfall angeschlossene Kabel dürfen eine Länge von 3m nicht überschreiten Installation Beschädigung von Schaltkreisen Elektrostatische Entladu...

Page 35: ...ugabe von primären Schutz nicht ausreichenden Schutz um diese Schnittstellen metallisch mit OSP Verdrahtung verbinden Die intra Gebäude Port s des Gerätes oder einer Unterbaugruppe müssen abgeschirmte innerGebäudeVerkabelung Verdrahtung die an beiden Enden geerdet ist zu verwenden Betrieb Beschädigung des Blades Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Blades können zu Kurzschlüs...

Page 36: ...d können mit produktionsrelevanten Funktionen belegt sein Das Ändern dieser Schalter kann im normalen Betrieb Störungen auslösen Verstellen Sie nur solche Schalter die nicht mit Reserved gekennzeichnet sind Prüfen und ändern Sie die Einstellungen der nicht mit Reserved gekennzeichneten Schalter bevor Sie das Blade installieren Beschädigung des Blades Das Verstellen von Schaltern während des laufen...

Page 37: ...se ATCA 7490 Installation and Use 6806800U11F 37 Umweltschutz Entsorgen Sie alte Batterien und oder Blades Systemkomponenten RTMs stets gemäß der in Ihrem Land gültigen Gesetzgebung und den Empfehlungen des Herstellers ...

Page 38: ...ATCA 7490 Installation and Use 6806800U11F Sicherheitshinweise 38 ...

Page 39: ... with two DIMM slots per channel 2 DPC resulting in a total of 16 DIMM slots 8GB 16GB and 32GB DDR4 modules in Very Low Profile VLP available Single slot ATCA form factor 280mm x 322mm Direct CPU to PCIe interface providing 40 PCIe Gen3 lanes 8 Gbps Next generation communications platform from Intel codename Grantley with on board Intel C612 Wellsburg Platform Controller Hub PCH Dual Gb Ethernet A...

Page 40: ...Legal safety requirements CISPR 22 CISPR 24 EN 55022 EN 55024 EN 55032 EN 300386 FCC Part 15 Legal EMC requirements on system level predefined Artesyn Embedded Technologies system ISO 8601 Y2K compliance ETSI EN 300019 series Telcordia SR 3580 NEBS GR 63 CORE NEBS GR 1089 CORE Telecom specific market requirements for environment EMC and safety NEBS Level 3 Product is designed to support NEBS level...

Page 41: ...inside the shelf For example at the backplane or the shelf has to provide a possibility to lead Logic Ground out of the shelf for external connection to Central Office Ground For further information refer to Telcordia GR 1089 CORE section 9 8 2 requirement R9 14 The product has been designed to meet the directive on the restriction of the use of certain hazardous substances in electrical and elect...

Page 42: ...Use 6806800U11F 42 1 4 Product Identification The following figure shows the location of the QR code and Serial Number of the product Figure 1 1 Location of Serial Number and QR Code QR Code and Serial Number Artesyn internal part number PCA ...

Page 43: ...signed for NEBS L3 ETSI No memory is installed Table 1 4 Blade Accessories Accessory Description ATCA 7XMEM 2133 8G 8GB DDR4 2133 VLP memory module for the ATCA 748X and ATCA 749X product series ATCA 7XMEM 2133 16G 16GB DDR4 2133 VLP memory module for the ATCA 748X and ATCA 749X product series ATCA 7XMEM 2400 8G 8GB DDR4 2400 VLP memory module for the ATCA 749X product series ATCA 7XMEM 2400 16G 1...

Page 44: ...Introduction ATCA 7490 Installation and Use 6806800U11F 44 ...

Page 45: ...ng the Blade Shipment Inspection To inspect the shipment perform the following steps 1 Verify that you have received all items of your shipment One ATCA 7490 blade One printed copy of Quick Start Guide One printed copy of Safety Notes Summary Any optional items ordered Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life ...

Page 46: ... the surrounding of the blade within the user environment The ATCA 7490 0GB HEL and ATCA 7490 0GB HEL products support the specified temperature conditions in a shelf with the airflow characteristics meeting at least the CP TA Class B 4 cooling profile The ATCA 7490 0GB HF and ATCA 7490 0GB HC products support the specified temperature conditions in a shelf with the airflow characteristics meeting...

Page 47: ...n 5 C 41 F to 40 C 104 F according to Telcordia GR 63 CORE NEBS and ETSI EN 300 019 1 3 Class 3 1 Exceptional Operation 5 C 23 F to 55 C 131 F according to Telcordia GR 63 CORE NEBS Note This exceeds ETSI EN 300 019 1 3 Class 3 1E requirements 5 C to 45 C 40 C 40 F to 70 C 158 F according to Telcordia GR 63 CORE NEBS and ETSI EN 300 019 1 2 Class 2 3 Note This exceeds ETSI EN 300 019 1 1 Class 1 2...

Page 48: ...tave minute according to Telcordia GR 63 CORE 5 20 Hz at 0 01 g2 Hz according to Telcordia GR 63 core and ETSI EN 300 019 2 2 20 200 Hz at 3 dB octave Hz according to Telcordia GR 63 core and ETSI EN 300 019 2 2 Random 5 20Hz at 1 m2 s3 Random 20 200Hz at 3 m2 s3 Shock Half sine 11 ms 30 m s2 Blade level packaging Half sine 6 ms at 180 m s2 Free Fall 1 2 m packaged according to ETSI 300 019 2 2 10...

Page 49: ...ture during blade operation To guarantee proper blade operation and to ensure safety you have to make sure that the temperatures at the locations specified in the Figure 2 1 are not exceeded If not stated otherwise the temperatures should be measured by placing a sensor exactly at the given locations Figure 2 1 Location of Critical Temperature Spots Blade Top Side Temperature Spot 2 48 V to 12 V D...

Page 50: ...lade In the Table 2 3 on page 51 you will find typical examples of power requirements with and without accessories installed For information on the accessories power requirements refer to the documentation delivered together with the respective accessory or consult your local Artesyn representative for further details The blade must be connected to a TNV 2 or a safety extra low voltage SELV circui...

Page 51: ...th RTM ATCA 749X 345W 256W Without any RTM 295W 206W The power consumption has been measured using specific boards in a configuration considered to represent the worst case maximum memory population 3x MO297 SSD modules and QSFPs and with software simultaneously exercising as many functions and interfaces as possible This includes a particular load software provided by Intel designed to stress the...

Page 52: ...ut FPGA ZONE 3 P30 P31 P32 P22 P20 P23 ZONE 1 J21 DIMM 1 J22 DIMM 2 J23 DIMM 3 J24 DIMM 4 Intel C612 PCH Wellsburg Intel i350 Powerville MO 297 Carrier 48V to 12V DCDC J15 DIMM 5 J16 DIMM 6 J17 DIMM 7 J18 DIMM 8 J14 DIMM 4 J13 DIMM 3 J12 DIMM 2 J11 DIMM 1 ATCA PIM ZONE 2 Base and Fabric IF Intel FM 10000 ZONE 2 Update Channel RTM 12V Power J25 DIMM 5 J26 DIMM 6 J27 DIMM 7 J28 DIMM 8 CPU 1 CPU 0 P3...

Page 53: ...ssembled in volume production Switches reside on the component side 1 and are not covered by any other component Their location is shown in the following figure Figure 2 3 Switch Location Bottom Side of the Blade Table 2 4 Switch SW1 settings Switch Function Default SW1 1 A2F200 JTAG_SEL strap OFF JTAG to Fabric Default ON JTAG to CPU Core OFF A2F200 JTAGSEL SW1 2 BIOS Image Swap OFF Default Image...

Page 54: ...ns always SW2 2 SW2 2IPMC Debug Console Routing OFF IPMC Debug Console at 3 pin Header ON IPMC Debug Console at Faceplate instead of FPGA COM OFF IPMC Debug Console TTL level routing OFF IPMC Debug Consoleat3 pinHeader SW2 3 FPGA_PROM_SEL OFF 0 default PROM ON 1 Backup Recovery PROM OFF Use standard download PROM or redundant download PROM for FPGA configuration SW2 4 OFF Reset push button enabled...

Page 55: ...ory size to your needs The corresponding installation removal procedures are described in this section For the location of the DIMM Memory modules see Figure 2 2 on page 52 SW3 2 SW3 2 controls Boot flash select if SW3 1 is ON OFF Boot from Default SPI Boot Flash device ON Boot from Recovery SPI Boot Flash device OFF OFF Boot from Default SPI Boot Flash device SW3 3 Debug Output to Serial Console ...

Page 56: ...econdary CPU 0 A J11 J12 B J13 J14 C J15 J16 D J17 J18 CPU 1 E J21 J22 F J23 J24 G J25 J26 H J27 J28 For optimal performance all memory channels A through H should be populated and also a balanced DIMM configuration is recommended that is every memory channel using the same type and amount of DIMMs In case of using only one DIMM per channel make sure that you use only primary sockets and leave the...

Page 57: ...ed the locks automatically close 4 If applicable repeat the steps 2 to 3 to install further modules Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life Before touching the module or electronic components make sure you are working in an ESD safe environment Damage of Circuits Electrostatic discharge and incorrect module ...

Page 58: ...SSD Carrier and MO297 SSD Modules ATCA 7490 provides a modular solution for up to three MO297 A compliant SSDs Each SSD is connected to the Intel C612 PCH via a SATA interface The modular approach consists of a riser card which provides up to three sockets for SSDs and the MO297 A compliant SSDs The SSD module is an accessory kit and is not part of the default ATCA 7490 For more information about ...

Page 59: ...nector with two fingers to prevent damage to the connector 3 Fasten the SSD module to the blade using the screws supplied with the ACC kit 4 Reinstall the blade into the system as described in Installing and Removing the Blade on page 60 The additional resource either memory or SATA SSD will be detected automatically during the boot up sequence Damage of Circuits Electrostatic discharge and incorr...

Page 60: ...SSD module from the blade 4 Reinstall the blade into the system as described in Installing and Removing the Blade on page 60 2 6 Installing and Removing the Blade The blade is fully compatible to the AdvancedTCA standard and is designed to be used in AdvancedTCA shelves Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their lif...

Page 61: ...red on you can disregard the blue LED and skip the respective step In this case it is purely a mechanical installation Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or electronic components make sure that you are working in an ESD safe environment Blade Malfunctioning Incorrect blade insta...

Page 62: ...and backplane connectors for damage or bent pins before attempting to insert a blade If any connector damage or pin damage is observed stop inserting the blade and send the damaged item to proper repair channels 2 Slide the latch into the release position and pull out the handle outward to unlatch the handle from the faceplate Do not pull the handle fully outward Latch Handle ...

Page 63: ...he blade into the shelf until you feel resistance Continue to push the blade gently until the blade connectors engage 5 Fully insert the blade and push the handle towards the faceplate The latch automatically slides inwards and locks the handle If your shelf is powered as soon as the blade is connected to the backplane power pins the blue LED is illuminated If you feel that you need an abnormal am...

Page 64: ...AdvancedTCA system In case you installed the board and closed the handle and latch but the blue LED does not turn on recheck the position of the latch of the hot swap handle lower one and make sure it slit inwards and locked the handle If an RTM is connected to the front blade make sure that the handles of both the RTM and the front blade are closed in order to power up the blade s payload Damage ...

Page 65: ...rd Do not pull the handle fully outward The blue LED starts blinking indicates that the blade power down process is ongoing 2 Wait until the blue LED is illuminated permanently Loosen the screws of the faceplate then unlatch both the handles and pull the handle fully outward until the blade is detached from the shelf 3 Remove the faceplate cables if applicable 4 Remove the blade from the shelf If ...

Page 66: ...Hardware Preparation and Installation ATCA 7490 Installation and Use 6806800U11F 66 ...

Page 67: ...formation about the Controls Indicators and Connectors associated with the ATCA 7490 blade 3 1 Faceplate The following figure illustrates the connectors controls and LEDs available on the ATCA 7490 faceplate Figure 3 1 Faceplate Handle Ethernet 1 COM 1 2x USB 3 0 Handle Reset U1 U2 U3 I S A T T O O S H S Ethernet 2 ...

Page 68: ...the IPMC Note This LED indicates the payload power status both in the early power state and the normal blade operation Off Payload power is disabled Note This LED is multicolored red green yellow and is programmable by IPMC ATN Amber ThisLEDiscontrolledbyhigherlayersoftware suchasmiddlewareor a user application ETH Status LEDs The Ethernet connector provides two status LEDs Link upper Green Link i...

Page 69: ... COM1 2x Ethernet 2x USB 3 0 IPMC Debug Console Connector P9 H S FRU State Machine During blade installation Permanently blue On board IPMC powers up Blinking blue Blade communicates with shelf manager OFF Blade is active During blade removal Blinking blue Blade notifies shelf manager of its desire to deactivate Permanently blue Blade is ready to be extracted Table 3 1 Faceplate LEDs continued LED...

Page 70: ...serial redirection feature uses COM1 as access interface Therefore swapping the serial interfaces via SW2 1 also changes the serial connector that you need to access to make use of the serial redirection feature The pinout of the serial interface connector is shown below The pinout in the following table is used according to the Cisco like Pinout The pins which are unconnected are marked as n c IP...

Page 71: ...own in the Figure 3 3 3 1 3 3 USB Connectors The blade provides two USB 3 0 connectors at its faceplate and one USB at RTM zone 3 interface The USB connectors at faceplate are compliant to the USB 3 0 standard and correspond to the blade s USB interfaces 3 and 4 The USB at RTM interface is compliant to USB 2 0 4 GND 5 GND 6 COM1_RS232_RXD 7 n c 8 n c Table 3 2 RJ45 female Serial Console Connector ...

Page 72: ...eader with GND TXD andRXDpinsrespectively ThepinoutofIPMCDebugSerialInterfaceisshowninthe following figure Figure 3 4 USB Connector Pinout Attaching a device to the front panel USB ports that exceeds the maximum USB current rating of 900mA for USB 3 0 and 500mA for USB 2 0 ports respectively will result in the ATCA 7490 protecting itself through a controlled board shutdown Figure 3 5 IPMC Debug Co...

Page 73: ...the MO297 SSD module carrier connector on board 3 2 1 MO297 SSD Module Carrier Connector The MO297 SSD module carrier Riser card connects three SATA interfaces of the Intel C612 PCH to three slots of standard MO297 type SSD flash discs This carries the following types of signals 3 SATA port from PCH Power supply 5V and 3 3V ...

Page 74: ...s and Connectors ATCA 7490 Installation and Use 6806800U11F 74 The location of the MO297 SSD module carrier or riser card is shown in the following figure Figure 3 6 Location of MO297 SSD Module Connector MO 297 Carrier ...

Page 75: ...97 SSD Module Carrier Connector Pinout Table 3 3 Signal Segment Pinout Pin Number Function Description S1 GND 2nd mate S2 A Differential signal Pair A S3 A S4 GND 2nd mate S5 B Differential signal Pair B S6 B S7 GND 2nd mate Table 3 4 Power Segment Pinout Pin Number Function P1 Not used 3 3V P2 Not used 3 3V P3 Not used 3 3V Pre Charge P4 GND P5 GND P6 GND ...

Page 76: ...tors ATCA 7490 Installation and Use 6806800U11F 76 P7 5V Pre Charge P8 5V P9 5V P10 GND P11 Reserved P12 GND P13 Not used 12V Pre Charge P14 Not used 12V P15 Not used 12V Table 3 4 Power Segment Pinout continued Pin Number Function ...

Page 77: ...connectors reside in three zones 1 to 3 as specified by the AdvancedTCA standard and are called P10 P20 P22 and P23 P30 P31 P32 P33 and P40 The pinouts of all these connectors are given in this section Figure 3 8 Location of AdvancedTCA Connectors P30 P31 P32 P22 P20 P23 ZONE 1 P40 P10 P33 ZONE 3 ZONE 2 Update Channel ZONE 2 Base and Fabric IF ...

Page 78: ...r residing in zone 1 is called P10 and it carries the following signals Power feed for the blade VM48_x_CON and RTN_x_CON Power enable ENABLE_x IPMB bus signals IPMB0_x_yyy Geographic address signals HAx Ground signals SHELF_GND and GND Reserved signals Figure 3 9 P10 Backplane Connector Pinout ...

Page 79: ...ls they are terminated on the blade and marked as TERM_ in the following pinouts In all other cases the pins are unconnected and consequently marked as n c The pinouts of P20 and P23 are as follows Figure 3 10 P20 Backplane Connector Pinout Rows A to D 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 a b c d a b c d e f g h CLK1A_P RRC_EPL4_TX3_P RRC_EPL4_TX1_P POWERVILLE_GE2_TX_P n c CLK1A_M RRC_EPL4_TX...

Page 80: ... n c CLK2B_M n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c RRC_EPL4_TX0_P RRC_EPL4_TX0_M RRC_EPL4_RX0_P RRC_EPL4_RX0_M 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 a b c d a b c d e f g h n c n c n c n c FAB_CH3_TX0_P n c n c n c n c FAB_CH3_TX0_M n c n c n c n c FAB_CH3_RX0_P n c n c n c FAB_CH3_RX0_M n c FAB_CH3_TX2_P FAB_CH3_TX2_M FAB_CH4_TX2_P n c...

Page 81: ...o D 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 e f g h a b c d e f g h n c n c n c n c n c n c n c n c FAB_CH4_TX1_P FAB_CH4_TX3_P n c n c FAB_CH4_TX1_M FAB_CH4_RX3_M n c n c FAB_CH4_RX1_P FAB_CH4_RX3_P n c n c FAB_CH4_RX1_M FAB_CH4_TX3_M n c n c n c n c n c n c n c n c n c n c FAB_CH3_TX3_P FAB_CH3_TX3_M FAB_CH3_RX3_P FAB_CH3_RX3_M FAB_CH3_TX1_P FAB_CH3_TX1_M FAB_CH3_RX1_P FAB_CH3_RX1_M ...

Page 82: ...P32 They are used to connect an RTM to the blade and carry the following signals Serial RS232_x_yyyy Serial ATA SATAx_yyy USB USBxy PCI Express PCIEx_yyy IPMI IPMB1_xxx ISMB_xxx Power VP12_RTM V3P3_RTM VP5_RTM General control signals BD_PRESENTx RTM_PRSNT_N RTM_RST_KEY RTM_RST Figure 3 15 P23 Backplane Connector Pinout Rows E to H ...

Page 83: ...PI_CS_N RSVD RTM_IPMB_SCL _149_SERIAL_RTM_RXD n c _149_SERIAL_RTM_TXD n c n c n c n c n c RSVD RSVD RSVD RSVD RSVD RSVD RSVD RTM_PS1_N gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd n c 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 e f g h a b c d e f g h n c RSVD _149_RTM_MOSI n c RSVD RSVD SATA6G_P3_RX_DN RTM_IPMB_SDA _149_RTM_MISO SATA6G_P3_RX_DP gnd RSVD n c n c RSVD _149_RTM_I2C_CLK ...

Page 84: ...X_N 6 PCIE_CPU1_P3_RX_P 7 PCIE_CPU1_P3_RX_P 4 PCIE_CPU1_P3_RX_N 4 CLK100_RTM_CPU1PORT3AB _DP gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd PCIE_CPU1_P3_RX_P 2 n c n c 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 e f g h a b c d e f g h PCIE_CPU1_P3_RX_N 15 PCIE_CPU1_P3_RX_N 11 PCIE_CPU1_P3_RX_N 13 PCIE_CPU1_P3_RX_N 9 PCIE_CPU1_P3_RX_N 7 PCIE_CPU1_P3_RX_N 5 CLK100_RTM_CPU1PORT3CD _DN PCI...

Page 85: ..._RX_M 1 PCIE_PORT9_RX_P 0 PCIE_PORT9_RX_P 3 PCIE_PORT9_RX_M 3 CLK100_RTMPCIE7_DP gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd PCIE_PORT10_RX_P 1 n c n c 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 e f g h a b c d e f g h PCIE_PORT7_RX_M 0 PCIE_PORT8_RX_M 0 PCIE_PORT7_RX_M 2 PCIE_PORT8_RX_M 2 PCIE_PORT9_RX_M 0 PCIE_PORT9_RX_M 2 CLK100_RTMPCIE8_DN PCIE_PORT9_RX_P 2 gnd PCIE_PORT8_TX_M 1...

Page 86: ...0_P RRC_EPL8_TX0_M RRC_EPL7_TX2_P RRC_EPL7_TX0_M RRC_EPL6_TX2_P RRC_EPL8_TX2_M RRC_EPL7_TX2_M RRC_EPL6_TX2_M RRC_EPL8_TX1_P RRC_EPL7_TX1_P gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 e f g h a b c d e f g h _147_RRC_RTM_I2C_DAT RRC_EPL5_TX1_M RRC_EPL6_TX1_M RSVD _147_RRC_RTM_I2C_CLK RRC_EPL5_TX3_M RRC_EPL5_RX0_M RRC_EPL6_RX0_M n c RRC_EPL8_TX3_...

Page 87: ...cators and Connectors ATCA 7490 Installation and Use 6806800U11F 87 B1 RTM_VP12 B2 B3 B4 C1 V3P3_MGMT_RTM G C2 C3 C4 D1 GND D2 D3 D4 E1 RTM_VP12 E2 E3 E4 Table 3 5 P40 Backplane Connector Pinout continued Pin Signal ...

Page 88: ...Controls Indicators and Connectors ATCA 7490 Installation and Use 6806800U11F 88 ...

Page 89: ... paths are used Figure 4 1 ATCA 7490 Block Diagram I O Subsystem USB Console Serial Intel Xeon Processor E5 2600 v4 Family Intel Xeon Processor E5 2600 v4 Family 1000 Base T 1000 Base T USB 4x GbE Zone 3 Rear I O Front Bezel 8x RDIMMs 8x RDIMMs USB 3 0 USB 3 0 GbE Base Fabric GbE Base Fabric Intel FM1000 Switch QPI x16 PCIe Gen 3 x16 PCIe Gen 3 IPMC Zone 2 Zone 3 Zone 2 Zone 1 SlimSATA x3 SATA 3 x...

Page 90: ...T s Each processor provides an integrated 4 channel DDR4 Memory Controller IMC supporting up to DDR4 2400 4 3 DDR4 Main Memory The blade provides two CPUs which has four channels of independent DDR4 memory on each CPU On each of the eight DDR4 channels the blade provides two DIMM sockets The Joint Electron Device Engineering Council JEDEC specification defines a DDR4 socket with 288 pins Registere...

Page 91: ...form Controller Hub Intel C612 Wellsburg The Next Generation Communications Platform Controller Hub codename Wellsburg Intel C612 PCH provides access between processors and the I O subsystem The PCH connects to CPU 0 through Intel DMI2 0 PCH I O controller connected to DMI2 interface of CPU 0 ATCA 7490 supports Intel Hybrid Clocking Mode through the Intel C612 PCH controller By default the Spread ...

Page 92: ...nput and A20GATE INIT3_3V CPUPWRGD PMSYNC PECI Two stage Watchdog timer WDT D31 F7 SPI Interface Boot Flash LPC Keyboard Controller Style KCS Interface Up to 10 serial ATA SATA controllers 6Gb s of which four are used on ATCA 7490 Six USB 3 0 and eight PCIe 2 0 interfaces of which 2 2 are used on ATCA 7490 Power management support D31 F0 including ACPI S3 state support suspend to RAM and Managemen...

Page 93: ...from primary flash SPI 0 fails a hardware mechanism automatically changes the flash device select logic to boot from the recovery flash SPI 1 The image that the processor will boot from after next reset is determined by the IPMC It can be selected via dedicated IPMI OEM command For more information refer to the section System Boot Options Commands on page 263 4 5 ATCA Fabric IF Ethernet The ATCA 7...

Page 94: ... of Intel FM10000 is connected to the ATCA Update channel providing 10G 40G Ethernet ATCA 7490 provides following mapping for PICMG3 0 Update channels Update Channel 0 Optional i350 1000Base KX Interface Update Channel 1 4 RC EPL Port 4 either 1x 40GBASE KR4 or 4x 10GBASE KR PICMG Update channels are backplane connections between pairs of front cards that operate on a redundant basis Application s...

Page 95: ...EPL4_TX1_P B3 RRC_EPL4_TX1_M C3 RRC_EPL4_RX1_P D3 RRC_EPL4_RX1_M E3 RRC_EPL4_TX2_P F3 RRC_EPL4_TX2_M G3 RRC_EPL4_RX2_P H3 RRC_EPL4_RX2_M A4 POWERVILLE_GE2_TX_P B4 POWERVILLE_GE2_TX_N C4 POWERVILLE_GE2_RX_P D4 POWERVILLE_GE2_RX_N E4 RRC_EPL4_TX0_P F4 RRC_EPL4_TX0_M G4 RRC_EPL4_RX0_P H4 RRC_EPL4_RX0_M Table 4 1 P20 Backplane Connector Pinout continued Pin Signal ...

Page 96: ...cket LGA2011 3 socket assembly The maximum thermal design power used by Intel Broadwell EP is 75 W The thermal resistance of the processor heat sink including interface material guarantees a proper cooling in the system The heat sink fixture withstands shock and vibration tests 4 9 BIOS ATCA 7490 provides a BIOS firmware that is stored in flash memory It can be updated remotely via Ethernet or loc...

Page 97: ...re sensors and monitoring logic of the Power Input Module PIM Figure 4 2 Master Only I2C Bus Architecture Table 4 2 IPMI I2C Bus Address Map private I2C bus Device Name Device Type Location I2C Controller SMBAddress hex IPMC Sensor 12 Inlet Temp LM75 ATCA 7490 IPMB L1 90 U44 SEL A2h U47 PCA9557 38h U122 PCA9555 4Ah U48 PCA9555 48h U43 FRU A0h U8 FPGA FEh MO I2C IPMB L1 SOL I2C A2F200 A2F200_MO_SCL...

Page 98: ...MB L1 50 FRU EEPROM 24C512 ATCA 7490 Atmel A2F200 Master Only I2C A0 SEL EEPROM 24C512 ATCA 7490 Atmel A2F200 Master Only I2C A2 GLUE FPGA Lattice LFE2 6E ATCA 7490 Atmel A2F200 Master Only I2C FE IPMC GPI I O Expander 1 PCA9555 ATCA 7490 Atmel A2F200 Master Only I2C 48 IPMC GPI I O Expander 2 PCA9555 ATCA 7490 Atmel A2F200 Master Only I2C 4A IPMC GPI I O Expander 1 PCA9557 ATCA 7490 Atmel A2F200 ...

Page 99: ...e is also available on the faceplate serial connector It can be selected via specific IPMI OEM command See section Set Serial Output Command on page 282 4 12 Serial Over LAN Serial over LAN SOL enables suitably designed blades and servers to transparently redirect a serial character stream of a baseboard UART to from a remote client via LAN over RMCP sessions This enables users at remote consoles ...

Page 100: ...es the following interfaces and control elements Two USB 3 0 ports Two 10 1000 1000Base T Ethernet ports Serial console port to connect to either payload or IPMC serial I F Recessed reset button Out of Service In Service Attention and Hot Swap LEDs The blade design provides the possibility to cover unused faceplate elements like LEDs or push button behind a custom overlay foil 4 15 Faceplate Seria...

Page 101: ...e IF connection is normally routed to a 3 pin on board header RS232 The IPMC Debug monitor terminal output can also be routed to the faceplate The IPMC Debug Console is also available when the ATCA 7490 Payload is powered off Table 4 3 Faceplate Serial Interfaces SW2 1 Connection HIGH Switch 2 1 OFF Default Glue Logic FPGA COM1 to faceplate Glue Logic FPGA COM2 to RTM LOW or Switch 2 1 ON Glue Log...

Page 102: ... The Trusted Platform Module TPM is a specific protected and encapsulated microcontroller security chip used to defend the internal data structures against real intelligent attacks The nature of this security chip ensures that the information like keys password and digital certificatesstoredwithinareprotectedfromexternalsoftwareattacksandphysicaltheft With Using the keys it stores all cryptographi...

Page 103: ... down backup method uses a Super CAP with a 1 Farad capacity This provides 300 hours of RTC SRAM backup 4 20 SMBus Intel C612 PCH Wellsburg provides six SMBus interfaces Only four interfaces are used on ATCA 7490 as described in the Table 4 5 The Master SMBus interface of the Intel C612 PCH is connected to on board devices like Clock PLLs temperature sensors and so on An I2C Bus Repeater of type P...

Page 104: ... Figure 4 3 SMBus Architecture Intel 612 PCH PCH SMBUS MGMT Domain XDP CPU LM75 Lower 90h LM75 Upper 94h PIM 50h isol isol DB1900 DEh U223 DB600 D8h U252 MMA8451 38h P16 Header IPMB L1 Table 4 6 SMBus Address Map Device Name DeviceType Location SMBus Controller SMB Address hex SPD EEPROM NA DDR4 module CPU 0 memory controller AB A0 SPD EEPROM NA DDR4 module CPU 0 memory controller AB A8 ...

Page 105: ...controller EF A8 SPD EEPROM NA DDR4 module CPU 0 memory controller GH A0 SPD EEPROM NA DDR4 module CPU 0 memory controller GH A8 IPMC Sensor 12 Inlet Temp LM75 ATCA 7490 Intel C612 PCH 90 IPMC Sensor 13 Outlet Temp LM75 ATCA 7490 Intel C612 PCH 94 48V Power Interface Sensor PIM4328 ATCA 7490 Intel C612 PCH 50 CB1900Z clock buffer IDT 9ZX21901BKLF ATCA 7490 Intel C612 PCH D8 Table 4 6 SMBus Address...

Page 106: ...Functional Description ATCA 7490 Installation and Use 6806800U11F 106 ...

Page 107: ...external logic level Table 5 2 Register Access Type Access Description r Read only w Write only r w Read and write w1c Write 1 to clear ignore bit while reading r w1c Read and write 1 to clear write 0 has no effect r w1s Read and write 1 to set write 0 has no effect r w1t Read and write 1 to toggle write 0 has no effect LPC The prefix LPC signals that the access is restricted to the LPC interface ...

Page 108: ... and the address range REGISTERS and within the address ranges of COM1 or COM2 only when enabled during Super IO configuration are decoded by the LPC core 5 1 1 1 2 LPC Memory Decoding The LPC interface never responds to LPC memory accesses Table 5 3 LPC I O Register Map Overview Base Address Address Size Address Range Name Description 0x4E 2 SIW Super IO Configuration Registers for Index and Date...

Page 109: ... the LPC I O address 0x80 The two nibbles of the register are converted to 7 segment codes and are displayed as two hex values by two 7 segment LED displays The IPMC can read the POST code using the I2C interface and the I2C register address 0x7F The two 7 segment LED displays are also used for power failure indication Table 5 4 IPMC I2C Register Map SPI Address Range Address Range Name Descriptio...

Page 110: ...nfiguration State When the Super IO is not in the Configuration State reads return 0xFF and write data is ignored 5 1 3 1 Entering the Configuration State The device enters the Configuration State by the following contiguous sequence 1 Write 80H to Configuration Index Port 2 Write 86H to Configuration Index Port 5 1 3 2 Existing the Configuration State The device exits the Configuration State by t...

Page 111: ... locations Reads to reserved registers may return non zero values Writes to reserved locations may cause system failure 5 1 3 4 1 Global Control Configuration Registers The Super IO Global Registers lie in the address range 0x00 0x2F All eight bits of the ADDRESS Port are used for register selection All unimplemented registers and bits ignore writes and return zero when read The INDEX PORT is used...

Page 112: ...Serial Port 1 0x05 Logical Device 5 UART2 Serial Port 2 A write to this register selects the current logical device This allows access to the control and configuration registers for each logical device 0 LPC r w Table 5 10 Super IO Device Identification Register Index Address 0x20 Bit Description Default Access 7 0 Device ID 0x0 LPC r Table 5 11 Super IO Device Revision Register Index Address 0x21...

Page 113: ...d 0 LPC r Table 5 13 Global Super IO SERIRQ and Pre divide Control Register Index Address 0x29 Bit Description Default Access 0 SERIRQ enable 0 disabled Serial interrupts disabled 1 enabled Logical devices participate in interrupt generations 0 LPC r w 1 SERIRQ Mode 1 Continuous Mode 1 LPC r 3 2 UART Clock pre divide 00 divide by 1 01 divide by 8 10 divide by 26 CLK_UART is 48 MHz 11 reserved 0 LP...

Page 114: ...sed to select a specific logical device register These registersarethenaccessedthroughtheDATAPORT TheLogicalDeviceregistersareaccessible only when the device is in the Configuration state The logical register addresses are shown in the tables below Table 5 14 Logical Device Configuration Register Summary Index Address Description 0x30 Enable 0x60 Base IO Address MSB 0x61 Base IO Address LSB 0x70 P...

Page 115: ... 16 Logical Device Base IO Address MSB Register Index Address 0x60 Bit Description Default Access 7 0 Logical Device Base IO Address MSB 0 LPC r w Table 5 17 Logical Device Base IO Address LSB Register Index Address 0x61 Bit Description Default Access 2 0 Bits 0 to 2 are read only Decode is on 8 Byte boundary 0 LPC r 7 3 Logical Device Base IO Address LSB Bits 3 to 7 0 LPC r w Table 5 18 Logical D...

Page 116: ... IRQ7 0x8 IRQ8 0x9 IRQ9 0xA IRQ10 0xB IRQ11 0xC IRQ12 0xD IRQ13 0xE IRQ14 0xF IRQ15 0 LPC r w 7 4 Reserved 0 LPC r An Interrupt is activated by enabling this device offset 0x30 setting this register to a non zero value and setting any combination of bits 0 4 in the corresponding UART IER and the occurrence of the corresponding UART event that means Modem Status Change Receiver Line Error Condition...

Page 117: ... Latch Bit DLAB which is the MOST significant bit of the Serial Line ControlRegister SCR affectstheselectionofcertainoftheUARTregisters TheDLABbitmust be set high by the system software to access the Baud Rate Generator Divisor Latches DLL and DLM Table 5 20 Logical Device 0x74 Reserved Register Index Address 0x74 Bit Description Default Access 7 0 Reserved 0x04 LPC r Table 5 21 Logical Device 0x7...

Page 118: ... value of the data byte at the top of the FIFO Table 5 23 UART Register Overview LPC IO Address DLAB Bit value Description Base 0 Receiver Buffer RBR Read Only Base 0 Transmitter Holding THR Write Only Base 1 0 Interrupt Enable Register IER Base 2 X Interrupt Identification Register IIR Read Only Base 2 X FIFO Control Register FCR Write Only Base 3 X Line Control Register LCR Base 4 X Modem Contro...

Page 119: ... a value in the Interrupt Identification Register Each of the four interrupt types can be disabledbyresettingtheappropriatebitoftheIERregister Similarly bysettingtheappropriate bits selected interrupts can be enabled Table 5 25 Transmitter Holding Register THR if DLAB 0 LPC IO Address Base Bit Description Default Access 7 0 Transmitter Holding register THR Undef LPC w Table 5 26 Interrupt Enable R...

Page 120: ...e Register IER if DLAB 0 continued LPC IO Address Base 1 Bit Description Default Access Table 5 27 UART Interrupt Priorities2 Priority Level Interrupt Source 1 highest Receiver Line Status One or more error bits were set 2 Received Data is available In FIFO mode trigger level was reached in non FIFO mode RBR has data 2 Receiver Time out occurred It happens in FIFO mode only when there is data in t...

Page 121: ...Table 5 29 Interrupt Identification Register Decode Interrupt ID Interrupt Set Reset Function 3 0 Priority Type Source Reset Control 0b0001 None No Interrupt is pending 0b0110 1 Receiver Line Status Overrun Error Parity Error Framing Error Break Interrupt Reading the Line Status Register 0b0100 2 Received Data Available Non FIFO mode Receive Buffer is full Non FIFO mode Reading the Receiver Buffer...

Page 122: ...egister if the source of the interrupt or writing to the Transmitter FIFO 0b0000 4 Modem Status Clear to Send Data Set Ready Ring Indicator Received Line Signal Detect Reading the modem status register Table 5 29 Interrupt Identification Register Decode continued Interrupt ID Interrupt Set Reset Function 3 0 Priority Type Source Reset Control Table 5 30 FIFO Control Register FCR LPC IO Address Bas...

Page 123: ...ead capability simplifies system programming and eliminates the need for separate storage in system memory 3 Receiver Transmitter ready Not supported 0 LPC w 5 4 Reserved 0 LPC w 7 6 Receiver FIFO interrupt trigger level 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes 0 LPC w Table 5 30 FIFO Control Register FCR continued LPC IO Address Base 2 Bit Description Default Access Table 5 31 Line Control Reg...

Page 124: ...hecked as cleared When bits 3 and 5 are set and bit 4 is cleared the parity bit is transmitted and checked as set If bit 5 is cleared stick parity is disabled 1 Stick parity enabled 0 Stick parity disabled 0 LPC r w 6 Break control bit Bit 6 is set to force a break condition i e a condition where TXD is forced to the spacing cleared state When bit 6 is cleared the break condition is disabled and h...

Page 125: ...in high state 0 LPC r w 2 User output control signal OUT1 1 OUT1 output in high state 0 OUT1 output in low state Not supported 0 LPC r w 3 User output control signal OUT2 1 OUT2 output in high state 0 OUT2 output in low state Not supported 0 LPC r w 4 Local loop back diagnostic control When loop back is activated Transmitter TXD is set high Receiver RXD is disconnected Output of Transmitter Shift ...

Page 126: ...til software reads LSR even if the character in the FIFO is read and a new character is now at the top of the FIFO Bitsonethroughfouraretheerrorconditionsthatproduceareceiverlinestatusinterruptwhen any of the corresponding conditions are detected and the interrupt is enabled These bits are notclearedbyreadingtheerroneousbytefromtheFIFOorreceivebuffer Theyareclearedonly by reading LSR In FIFO mode ...

Page 127: ...data continues to fill the FIFO beyond the trigger level an overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register An overrun error is indicated to the CPU as soon as it happens The character in the shift register is overwritten but it is not transferred to the FIFO 1 Overrun error occurred 0 No overrun error 0 LPC r 2 Parity Erro...

Page 128: ...CPU reads the contents of the LSR In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the CPU when its associated character is at the top of the FIFO When a break occurs only one 0 character is loaded into the FIFO The next character transfer is enabled after RXD goes to the marking state for at least two Receiver CLK sa...

Page 129: ...MT indicator TEMT bit is set when the THR and the TSR are both empty When either the THR or the TSR contains a data character TEMT is cleared In the FIFO mode TEMT is set when the transmitter FIFO and shift register are both empty 1 THR Transmit FIFO TSR empty 0 THR Transmit FIFO TSR contains data 1 LPC r 7 FIFO data error In the FIFO mode LSR7 is set when there is at least one parity framing or b...

Page 130: ...When DDSR is set and the modem status interrupt is enabled a modem status interrupt is generated 1 Change in state of DSR input since last read 0 No change in state of DSR input since last read 0 LPC r w 2 Trailing edge of the ring indicator TERI detector TERIindicatesthattheRI inputtothechiphaschangedfromalow to a high level When TERI is set and the modem status interrupt is enabled a modem statu...

Page 131: ...ding either of the divisor latches a 16 bit baud counter is immediately loaded This prevents long counts on initial load Access to the divisor latch can be done with a word write 6 Complement of the ring indicator RI input When the ACE is in the diagnostic test mode LOOP MCR4 1 this bit is equal to the MCR bit 2 OUT1 Not supported Ext LPC r 7 Complement of the data carrier detect DCD input When th...

Page 132: ...16X Divisor For example if the pre divider is 26 the UART_CLK is 1 8461538MHz When the divisor is 12 the baud rate is 9600 A divisor value of 0 in the Divisor Latch Register is not allowed Table 5 36 Divisor Latch LSB Register DLL if DLAB 1 PC IO Address Base Bit Description Default Access 7 0 Divisor Latch LSB DLL Undef LPC r w Table 5 37 Divisor Latch MSB Register DLM if DLAB 1 LPC IO Address Ba...

Page 133: ...e FPGA registers may be accessed via IPMC Private I2C transactions Slave address 0x7F See Table 5 38 FPGA Register Map Overview An IPMC write access to an address not listed in this table or marked with an in the IPMC I2C column isignored A corresponding read access delivers always zero The address offsets not mentioned below are not used and reserved for future extensions A reserved register is r...

Page 134: ...See Table 5 53 0x11 r w r Reset Mask Register See Table 5 54 0x12 r w1c r BIOS IPMC Watchdog Timeout Register See Table 5 57 0x13 w BIOS Push Button Enable Register See Table 5 58 0x14 r w1c r OS Reset Source Register See Table 5 59 0x15 r w1c r OS IPMC Watchdog Timeout Register See Table 5 60 0x16 r w IPMC Watchdog Timeout Register See Table 5 61 0x17 r w1c IPMC Reset Source Register See Table 5 ...

Page 135: ...g I2C IO Expander Registers See Chapter 5 CPU0 Hot Plug I2C IO Expander Registers 0x40 r r w Flash Status Register See Table 5 82 0x41 r w r PCH Output Enable Register See Table 5 83 0x42 r w RTM SPI Address Command Register See Table 5 84 0x43 r w RTM SPI Write Register Table 5 85 RTM SPI Read Register See Table 5 86 0x48 r w r Update Channel Equalization Control Register See Table 5 87 0x4A r w ...

Page 136: ... 5 100 0x68 0x69 r w Telecom Clock Monitor Lower Limit Register See Table 5 101 0x6A 0x6B r w Telecom Clock Monitor Upper Limit Register See Table 5 102 0x74 r w r BIOS Version Register 1 See Table 5 103 0x75 r w r BIOS Version Register 2 See Table 5 104 0x76 r w r BIOS Version Register 3 See Table 5 105 0x78 r r w IPMC BIOS Communication Register 1 See Table 5 106 0x79 r r w IPMC BIOS Communicati...

Page 137: ...ontrol Register BIOS sets the corresponding bit which is used for serial redirection The IPMC uses this information to route the corresponding port to serial IPMC interface in case of SOL Table 5 39 Module Identification Register Address Offset 0x00 Bit Description Default Access 15 0 ATCA 7490 Blade Module Identification 0x7490 r Table 5 40 FPGA Version Register Address Offset 0x02 Bit Descriptio...

Page 138: ...n 0 LPC r w IPMC r 1 COM2 use for serial redirection 0 COM2 not used for serial redirection 1 COM2 used for serial redirection 0 LPC r w IPMC r 7 2 Reserved 0 r When both control bits are enabled bit 1 is ignored Serial over LAN is done through NCSI from IPMC MAC to PCH Therefore this register is implemented as backup option Table 5 42 Serial over LAN Control Register Address Offset 0x04 Bit Descr...

Page 139: ...o Faceplate Note Setting may be overwritten by IPMC Software controlling Bit 4 Ext SW2 1 0 OFF 1 ON r 1 Inverted level of signal IPMC_SER_2_HEADER which is controlled by switch SW2 2 0 IPMC Serial Debug Interface to 3 Pin Header 1 IPMC Serial Debug Interface to Faceplate Note Setting may be overwritten by IPMC Software controlling Bit 5 Ext SW2 2 0 OFF 1 ON r 3 2 Reserved 0 r 4 IPMC_COM_ROUTE_A 0 ...

Page 140: ... 5 1 13 1 ME Power Failure Registers When an ME failure occurs the red power failure LED signal PWR_FAIL_ starts blinking The LED is one second ON and one second OFF Table 5 44 IPMC Power Level Register Address Offset 0x06 Bit Description Default Access 7 0 IPMC Power Level IPMC writes a value which correspond to a defined power level PWR_GOOD 0 IPMC r w LPC r Table 5 45 IPMC Power Level Multiplie...

Page 141: ...7 ME Power Failure States Note Only valid with ME Failure Bit 7 set PWR_GOOD 0 IPMC r 6 3 Reserved 0 IPMC r 7 ME Failure ME state machine sampled a failing ME Power status 0 No ME Failure Normal ME operation 1 ME failure ME failure detected PWR_GOOD 0 IPMC r Table 5 47 ME Power Failure States State Coding State Name Description 0 ME_OFF Timeout ASW power good for more than 45ms also ME is in ME_OF...

Page 142: ...8_EN_ is deasserted Table 5 48 ME Power Failure Cause Register Address Offset 0x09 Bit Description Default Access 0 Active Sleep Well ASW power failure 0 No ASW power failure ASW power is as expected 1 ASW power failure ASW power has different value as expected Note Only valid when ME Failure Bit 7 of ME Power Failure State Register Table 5 49 is set PWR_GOOD 0 IPMC r 7 1 Reserved 0 IPMC r Table 5...

Page 143: ... failure detected PWR_GOOD 0 IPMC r Table 5 50 Payload Power Failure States State Coding State Name Description 0x2 CLK_ENABLE One or more voltages have failed which have been already enabled and sampled good 0x5 S0 One or more voltages have failed which have been already enabled and sampled good Other cause Thermtrip 0x6 S3 One or more of these voltages have failed 12V 5V aux VPP or VDD 0x8 TRACK...

Page 144: ...ready enabled and sampled good 0xC VP12_ON Timeout debug disabled after 280ms 12V or 5V aux voltages are not good 0xD VTT_ENABLE Timeout debug disabled after 280ms VTT voltages are not good Other cause One or more voltages have failed which have been already enabled and sampled good 0xE WAIT_100MS One or more voltages have failed which have been already enabled and sampled good 0x10 WAKE_UP Timeou...

Page 145: ...Power Failure Cause Register 2 Address Offset 0x0C Bit Description Default Access 0 12V power good failure signal PWRGD_VP12 0 No 12V power issue 1 12V power failure PWR_GOOD 0 IPMC r 1 5V aux power good failure signal PWRGD_VP5AUX 0 No 5V aux power issue 1 5V aux power failure PWR_GOOD 0 IPMC r 2 5V power good failure signal PWRGD_VP5 0 No 5V power issue 1 5V power failure PWR_GOOD 0 IPMC r 3 RRC...

Page 146: ...V and 1 05 power failure PWR_GOOD 0 IPMC r 6 2 5V power good failure signal PWRGD_V2P5 0 No 2 5V power issue 1 2 5V power failure PWR_GOOD 0 IPMC r 7 1 5V power good failure signal PWRGD_V1P5 0 No 1 5V power issue 1 1 5V power failure PWR_GOOD 0 IPMC r Table 5 53 Payload Power Failure Cause Register 3 Address Offset 0x0D Bit Description Default Access 0 VPP CPU0 power good failure signal PWRGD_PVP...

Page 147: ... 0 No VTT CPU0 power issue 1 VTT CPU0 power failure PWR_GOOD 0 IPMC r 5 VTT CPU1 power good failure signal PWRGD_VTT_EFGH 0 No VTT CPU1 power issue 1 VTT CPU1 power failure PWR_GOOD 0 IPMC r 6 VCCIN CPU0 power good failure signal PWRGD_PVCCIN_CPU0 0 No VCCIN CPU0 power issue 1 VCCIN CPU0 power failure PWR_GOOD 0 IPMC r 7 VCCIN CPU1 power good failure signal PWRGD_PVCCIN_CPU1 0 No VCCIN CPU1 power ...

Page 148: ...MC r 2 Status of signal SLP_S3_ Ext IPMC r 3 Reserved 0 IPMC r 4 Status of signal CPU_PWRGD Ext IPMC r 5 Status of signal XDP_HOOK1_SEL Ext IPMC r 6 Status of signal XDP_PWRGD_RST_ Ext IPMC r 7 Status of signal XDP_CPU_SYSPWROK Ext IPMC r Table 5 55 ARTM Power Failure Register Address Offset 0x0F Bit Description Default Access 0 ARTM power failure 0 ARTM not powered or ARTM is on and running 1 ART...

Page 149: ...register bits one cannot determine the most recent reset source since more than one bit will be set The same situation will happen if two reset sources go active at the same time 6 4 ARTM Power Failure State Latched last ARTM state when failure occurred 0 IPMC r 7 Reserved 0 IPMC r Table 5 56 ARTM Power Failure States State Coding State Name Description 2 RTM_ON ARTM power has failed when ARTM was...

Page 150: ...d Table 5 57 BIOS Reset Source Register Address Offset 0x10 Bit Description Default Access 0 PWR_GOOD Payload Power on reset 1 Reset occurred PWR_GOOD 1 LPC r w1c IPMC r 1 XDPx reset request Any one of XDPx signal caused reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 2 PB_RST_ face plate push button reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 3 Reserved 0 r 4 RTM_PB_RST_ Reset key at RT...

Page 151: ...is OFF 0 SW2 4 is ON LPC r w 3 Reserved 0 r 4 RTM_PB_RST_ Reset key at RTM 1 enabled 0 disabled Ext FACE_PB_EN 1 SW2 4 is OFF 0 SW2 4 is ON LCP r w 7 5 Reserved 0 r Table 5 58 Reset Mask Register continued Address Offset 0x11 Bit Description Default Access OS should never write to this register Table 5 59 BIOS IPMC Watchdog Timeout Register Address Offset 0x12 Bit Description Default Access 0 BIOS...

Page 152: ...Reset Source Register A 1 in the register bit indicates that the associated reset has occurred If more than one reset occurs from different sources without clearing the corresponding register bits one cannot determine the most recent reset source since more than one bit will be set The same will happen if two reset sources go active at the same time After a timeout of 8s the resets are armed again...

Page 153: ...efault Access 0 PWR_GOOD Payload Power on reset 1 Reset occurred PWR_GOOD 1 LPC r w1c IPMC r 1 XDPx reset request Any one of XDPx signal caused reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 2 PB_RST_ faceplate push button reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 3 Reserved 0 r 4 RTM_PB_RST_ Reset key at RTM 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 5 Reserved 0 r 6 PCH_PLTRST_ re...

Page 154: ...eout Register Address Offset 0x15 Bit Description Default Access 0 OS IPMC Watchdog Timeout 1 IPMC Watchdog Timeout occurred PWR_GOOD 0 LPC r w1c IPMC r 1 OS IPMC Pre Timeout 1 IPMC Pre Timeout occurred PWR_GOOD 0 LPC r w1c IPMC r 7 2 Reserved 0 r IPMC needs to clear the IPMC watchdog timeout bit to arm IPMC watchdog timeout event recognition Table 5 63 IPMC Watchdog Timeout Register Address Offse...

Page 155: ...e time 1 IPMC Pre Timeout 0 No IPMC Pre Timeout 1 IPMC Pre Timeout occurred PWR_GOOD 0 IPMC r w 7 2 Reserved 0 r Table 5 63 IPMC Watchdog Timeout Register continued Address Offset 0x16 Bit Description Default Access Table 5 64 IPMC Reset Source Register Address Offset 0x17 Bit Description Default Access 0 PWR_GOOD Payload Power on reset 1 Reset occurred PWR_GOOD 1 IPMC r w1c 1 XDPx reset request A...

Page 156: ...urred PWR_GOOD 0 IPMC r w1c Table 5 64 IPMC Reset Source Register continued Address Offset 0x17 Bit Description Default Access IPMC version 1 2 0018 or higher is needed to clear the interrupt flag Otherwise the IPMC interrupt will always be active and produce infinite IPMC interrupts Table 5 65 IPMC Interrupt Status Register Address Offset 0x19 Bit Description Default Access 0 IPMC interrupt statu...

Page 157: ...H_ADR_IRQ_ signal is asserted When PCH signals completion with assertion of ADR_COMPLETE the Reset State Machine asserts PCH_SYS_RST_ If ADR is not enabled PCH_SYS_RST_ is generated immediately without the assertion of PCH_ADR_IRQ_ signal Table 5 66 DIMM ADR Feature Configuration Register Address Offset 0x18 Bit Description Default Access 0 ADR enable for Push button reset 1 ADR enabled 0 ADR disa...

Page 158: ...ADR Status Register Address Offset 0x1A Bit Description Default Access 0 IndicatesiftheADRfeatureisenabled GPIO37of Cavecreek 0 ADR disabled PCH_ADR_IRQ_ is driven high 1 ADR enabled PCH_ADR_IRQ_ is driven low PWR_GOOD 0 LPC r w1c IPMC r 7 1 Reserved 0 r Table 5 68 Reset Control Register Address Offset 0x1A Bit Description Default Access 0 Control Bit for BASE_PLTRST_ 0 Reset is deasserted Signal ...

Page 159: ... is driven high 1 Reset is asserted Signal is driven low 0 LPC r w IPMC r 6 Control Bit for RTM_PLTRST_ 0 Reset is deasserted Signal is driven high 1 Reset is asserted Signal is driven low 0 LPC r w IPMC r 7 Reserved 0 r Table 5 68 Reset Control Register continued Address Offset 0x1A Bit Description Default Access Table 5 69 CPU Control Register Address Offset 0x1E Bit Description Default Access 0...

Page 160: ...C can initiate a NMI Host can identify NMI comes from IPMC Table 5 70 S States Control Register Address Offset 0x1F Bit Description Default Access 0 SCI pulse generation Minimum low pulse width is 45ms 0 No action 1 Generate SCI low pulse Trigger S0 S3 transition IPMC w 1 PWRBTN pulse generation Minimum low pulse width is 32ms 0 No action 1 Generate PWRBTN low pulse Trigger S3 S5 S0 transition or ...

Page 161: ...ol and Status Registers The interrupt status registers indicate events of the interrupt input signals When an interrupt event occurred the corresponding status bit is read 1 Writing 1 of the corresponding bit clears the bit Table 5 71 NMI Generation Register Address Offset 0x20 Bit Description Default Access 7 0 NMI pulse generation Minimum pulse width is 175μs 0xA5 Generate NMI pulse all other va...

Page 162: ...o show how to clear the corresponding interrupt status bits Table 5 73 Internal Interrupt Status Register Address Offset 0x21 Bit Description Default Access 0 IPMC signals interrupt Host clears flag 0 LPC r 1wc IPMC generates host interrupt 0 no action 1 generate minimum 175μs interrupt pulse IPMC w 7 1 Reserved 0 r Table 5 74 Telecom Interrupt Status Register Address Offset 0x22 Bit Description D...

Page 163: ...tion Default Access 3 0 Telecom CLK_MONITOR_FINISHED interrupt enable Enable Disable interrupt for the corresponding Clock source 0 interrupt is disabled 1 Interrupt is enabled 0 LPC r w 7 4 Telecom CLK_MONITOR_OUT_OF_RANGE interrupt Enable Disable interrupt for the corresponding Clock source 0 interrupt is disabled 1 Interrupt is enabled 0 LPC r w Table 5 76 External Interrupt Status Register Add...

Page 164: ...ase all interrupt sources need to be of type level active low Each interrupt source has an Interrupt Mask and Map Register See Table 5 77 7 1 Reserved 0 r Table 5 76 External Interrupt Status Register continued Address Offset 0x24 Bit Signal Group Description Default Access Table 5 77 Address Map of Interrupt Mask and Map Registers Interrupt Source s Description Address Offset of Interrupt Mask IP...

Page 165: ...er 2 IRQ1 0x03 Frame number 3 IRQ2 SMI_ 0x04 Frame number 4 IRQ3 0x05 Frame number 5 IRQ4 0x06 Frame number 6 IRQ5 0x07 Frame number 7 IRQ6 0x08 Frame number 8 IRQ7 0x09 Frame number 9 IRQ8 0x0A Frame number 10 IRQ9 0x0B Frame number 11 IRQ1 0x0C Frame number 12 IRQ11 0x0D Frame number 13 IRQ12 0x0E Frame number 14 IRQ13 0x0F Frame number 15 IRQ14 0x10 Frame number 16 IRQ15 0x11 Frame number 17 IO...

Page 166: ...he Hot Plug Virtual Pin Port Register Table 5 79 Table 5 79 Hot Plug Virtual Pin Port Register Address Offset CPU0 Port 1 0x30 Port 2 0x31 Port 3 0x32 Port 4 0x33 CPU1 Port 1 0x38 Port 2 0x39 Port 3 0x3A Port 4 0x3B Bit Signal Name Direction Description Default Access 0 ATNLED Output This indicator is connected to the Attention LED on the baseboard For a precise definition refer to PCI ExpressBase...

Page 167: ... to mechanically hold the card in place and can be open closed manually Electromechanical latch is used to electro mechanically hold the card in place and is operated by software MRL is used for card edge and EMLSTS is used for SIOM form factors 1 IPMC r w LPC r 7 EMIL Output Electromechanical retention latch control output that opens or closes the retention latch on the board for thisslot Aretent...

Page 168: ...atus of the mechanical switches SW1 3 Signal BOOT_TSOP SW3 1 Signal BOOT_SEL_EN_ and SW3 2 Signal BOOT_DEFAULT Table 5 80 Address Control for PCA9555 Internal Register Address Offset CPU0 Device1 Slave address 0x20 0x34 CPU0 Device2 Slave address 0x21 0x36 CPU1 Device1 Slave address 0x20 0x3C CPU1 Device1 Slave address 0x21 0x3E Bit Description Default Access 2 0 Internal PCA9555 register address ...

Page 169: ...le 5 82 Flash Status Register Address Offset 0x40 Bit Description Default Access 0 CURRENT_BOOT_SELECT Current Boot Flash selection Is valid until next platform reset 0 r 3 1 Reserved 0 r 4 TSOP or PLCC Boot select Signal BOOT_TSOP 0 TSOP selected 1 PLCC selected Ext 0 SW1 3 OFF 1 SW1 3 ON r 5 Manual Boot Flash select enable Signal BOOT_SEL_EN_ 0 Signal BOOT_SELECT selects active boot flash 1 Swit...

Page 170: ...Registers The signals RTM_SPI_SCK RTM_SPI_SS_ RTM_SPI_MISO and RTM_SPI_MOSI are used to support a SPI master protocol The signal RTM_SPI_MISO is also used to signal an ARTM interrupt to the base board See Table 5 90 Table 5 83 PCH Output Enable Register Address Offset 0x41 Bit Description Default Access 0 PCH_RCIN_ enable 0 Disabled Signal is tri state 1 Enabled Drive pch_rcin 0 LPC r w 1 PCH_SCI_...

Page 171: ... the SPI device A write access to the RTM SPI Address Command Register with the Command Bit 1 Read starts a SPI read transaction This contains the data read from the SPI device Table 5 84 RTM SPI Address Command Register Address Offset 0x42 Bit Description Default Access 0 Command Bit 0 Write 1 Read 0 LPC r w 7 1 RTM SPI Address bits 6 0 0 LPC r w Table 5 85 RTM SPI Write Register Address Offset 0...

Page 172: ...lt Access 7 0 Update Channel Equalization code Not connected to output pins 0 LPC r w IPMC r Table 5 88 RTM USB Control Register Address Offset 0x4A Bit Description Access 0 Reserved 0 r 1 Disable Enable USB Port 2 to RTM 0 RTMUSB_ENABLE_ driven low Enabled 1 RTMUSB_ENABLE_ driven high Disabled PWR_GOOD 1 LPC r w IPMC r 7 2 Reserved 0 r Table 5 89 RTM Status Register Address Offset 0x4B Bit Descri...

Page 173: ...dge PV_BASE_1_INT_ 0 IPCM r w1c 7 2 Reserved 0 IPMC r Table 5 91 LED Control Register Address Offset 0x50 Bit Description Default Access 0 Control green LED output Signal LED_GREEN_ 0 LED_GREEN_ is driven high LED off 1 LED_GREEN_ is driven low LED on 0 r w 1 Control read LED output Signal LED_RED_ 0 LED_RED_ is driven high LED off 1 LED_RED_ is driven low LED on 0 r w 2 Control user LED output Si...

Page 174: ...1 Signal level of SW1 4 Connected to SW1 4 Ext r 3 2 Signal level of spare connections SPARE 2 1 Ext r 7 4 Reserved Ext r Table 5 93 CPU Presence Detection Register Address Offset 0x54 Bit Description Default Access 1 0 Reserved 0 r 2 CPU0 Presence Detection Status of signal CPU0_SKTOCC_ 0 CPU present in socket 1 CPU not present Socket is empty Ext r 3 CPU1 Presence Detection Status of signal CPU1...

Page 175: ...et 0x57 Bit Signal Description Default Access 0 CPU_ERR_ 0 CPU Error status signals Bit 0 Non critical Error Bit 1 Non fatal error operating system or firmware action required to contain and recover Bit 2 Fatal error system reset likely required to recover Ext r 1 CPU_ERR_ 1 Ext r 2 CPU_ERR_ 2 Ext r 7 3 Reserved 0 r Table 5 95 Supervised Telecom Clocks Reference List Number Name Description 0 SYSC...

Page 176: ... Register Address 0x60 Bit Description Default Access 3 0 Enable supervised Telecom Clock 0 to 3 Set corresponding bit enable monitoring 0 LPC r w 7 4 Reserved 0 r Table 5 97 Telecom Clock Monitor Status Register Address 0x61 Bit Description Default Access 3 0 Result available for supervised Telecom Clock 0 to 3 Corresponding bit is set when measurement has finished Clearing bit triggers new measu...

Page 177: ... to 3 is out of range Gate Mode Corresponding bit is set when the number of positive Clock edges within the selected time base is Lower limit or Upper limit Period Mode Corresponding bit is set when the Clock 0 Period within the selected time base is Lower limit or Upper limit Clearing bit triggers new sequence of measurements 0 LPC r w1c 7 4 Reserved 0 r Table 5 99 Telecom Clock Monitor Select Re...

Page 178: ...is open for 4096ms 15 Gate is open for 8192ms 16 Gate is open for 16384ms 17 and all others Gate is open for 32768ms 0 LPC r w Select Time base for clock supervision with Period Mode 0 Period Counter incremented with each master clock 1 Period Counter incremented with each 2nd master clock 2 Period Counter incremented with each 4th master clock 3 Period Counter incremented with each 8h master cloc...

Page 179: ...imer base 65535 Overflow Clock to fast for time base Period Mode 0 No clock edge sampled Clock to fast for time base 1 65534 Number of clocks during one supervised clock period 65535 Overflow Supervised clock to slow for time base Note Only valid when corresponding bit in Table 5 97 Telecom Clock Monitor Status Register is set 0 LPC r Table 5 102 Telecom Clock Monitor Lower Limit Register Address ...

Page 180: ... 98Telecom Clock Monitor Out of Range Register 0xFFFF LPC r w Table 5 104 BIOS Version Register 1 Address Offset 0x74 Bit Description Default Access 7 0 BIOS Version bits 0 to 7 0 LPC r w IPMC r Table 5 105 BIOS Version Register 2 Address Offset 0x75 Bit Description Default Access 7 0 BIOS Version bits 8 to 15 0 LPC r w IPMC r Table 5 106 BIOS Version Register 3 Address Offset 0x76 Bit Description...

Page 181: ...OD 0 LPC r w IPMC r w Table 5 108 IPMC BIOS Communication Register 2 Address Offset 0x7B Bit Description Default Access 7 0 IPMC BIOS Communication bits PWR_GOOD 0 LPC r w IPMC r w Table 5 109 IPMC BIOS Communication Register 3 Address Offset 0x7C Bit Description Default Access 7 0 IPMC BIOS Communication bits PWR_GOOD 0 LPC r w IPMC r w Table 5 110 LPC Scratch Register Address Offset 0x7D Bit Des...

Page 182: ...Maps and Registers ATCA 7490 Installation and Use 6806800U11F 182 Table 5 111 IPMC Scratch Register Address Offset 0x7E Bit Description Default Access 7 0 IPMC Scratch bits PWR_GOOD 0 IPMC r w LPC r ...

Page 183: ... page 264 The BIOS used on the blade is based on the Insyde UEFI BIOS with several Artesyn extensions integrated Its main features are Initialize CPU chipset and memory Initialize PCI devices Setup utility for setting configuration data IPMC support Serial console redirection for remote blade access Boot operation system The BIOS complies with the following specifications UEFI Specification 2 4 Pl...

Page 184: ... can be configured via a setup utility 6 1 1 Requirements for Serial Console Redirection For serial console redirection the following are required Terminal or terminal emulation which supports a VT100 mode NULL modem cable Terminal emulation programs such as TeraTermPro or Putty can be used 6 1 2 Default Access Parameters By default the blade can be accessed using the serial interface COM1 By defa...

Page 185: ...VT 100 8 data bits No parity 1 stop bit 6 1 3 Connecting to the Blade Procedure To connect to the blade using the serial console redirect feature 1 Configure terminal to communicate using the same parameters as in BIOS setup 2 Connect the terminal to NULL modem cable 3 Connect the NULL modem cable to COM port of the blade 4 Start up the blade 6 2 Changing Configuration Settings When the system is ...

Page 186: ...n at the bottom of the menu Additionally an item specific help is displayed on the right side of the window Figure 6 1 Main Menu Make sure BIOS is properly configured prior to installing the operating system and its drivers If you save changes in setup the next time the blade boots up BIOS configures the system according to the setup selections stored If those values cause the system boot to fail ...

Page 187: ...ll storage devices that are connected to the system for a valid GUID Partition Table GPT If there is a known boot loader found in the EFI System Partition a new entry is added to the boot order list For example if the EFI System Partition contains the EFI redhat grub efi file BIOS will add Red Hat Linux to the boot list In UEFI boot mode network devices are handled in the same way as in legacy mod...

Page 188: ...from the following devices sources Solid State Disk connected to the SATA interface available only when SSD SATA is assembled USB devices floppy CD ROM and hard disk PXE boot from Front Panel Ethernet Base Ethernet and Fabric Ethernet 6 3 4 Selecting the Boot Device To determine the device from which BIOS attempts to boot the following are the possibilities By setup to select a permanent order of ...

Page 189: ...Select Legacy Boot Order and or EFI Boot Order 3 Select the order of the devices from which BIOS attempts to boot the operating system Figure 6 2 Boot Device Priority If BIOS is not successful at booting from one device it tries to boot from the next device on the list When BIOS does not find any bootable device the board will be restarted by a cold reset ...

Page 190: ... Enter Boot Manager 3 Override existing boot sequence by selecting another boot device from the boot list Figure 6 3 Boot Menu If a selected legacy boot device does not load the operating system BIOS will reset the blade If an EFI boot device does not load the operating system it will return to the Boot Manager ...

Page 191: ...write capabilities of two or more hard drives working in unison to maximize the storage performance RAID 1 Mirroring a RAID 1 array contains two hard drives where the data between the two is mirrored in real time to provide good data reliability in the case of a single disk failure when one disk drive fails all data is immediately available on the other without any impact to the integrity of the d...

Page 192: ...on the selected Boot Type in Boot menu there are two different user interfaces to configure the RAID mode 6 4 2 2 RAID configuration for Legacy Boot Type For Legacy Boot Type and Dual Boot Type the Intel Rapid Store Technology Option ROM is executed by the BIOS To enter the configuration menu of the Option ROM the following key sequence has to be entered on the serial console ESC CTRL I or ESC TAB...

Page 193: ...age of the user interface shows the main menu with Disk Volume Information For creating a new RAID volume select 1 Create RAID Volume Figure 6 5 Intel Rapid Store Technology Option ROM main menu Figure 6 6 Intel Rapid Store Technology Option ROM create volume menu ...

Page 194: ... it press Enter 5 Unless for RAID 1 select the strip size with the up and down arrow keys and then press Enter 6 Select the volume capacity and press Enter The default value shows the maximum volume capacity for the selected disks 7 At the Create Volume prompt press Enter to create the volume Press Y key to confirm the volume creation 8 Exit the user interface by selection of the Exit option and p...

Page 195: ...the Rapid Store Technology driver 1 Enter the Boot Menu Front Page by pressing the F4 key 2 Select Device Manager from the Boot Menu Enter the Intel RSTe SATA Controller device The first page of the user interface shows the main menu with Disk Volume Information Figure 6 7 Device Manager ...

Page 196: ...on and Use 6806800U11F 196 For creating a new RAID volume select Create RAID Volume The following screen is displayed Figure 6 8 Intel Rapid Store Technology main menu Figure 6 9 Intel Rapid Store Technology create volume menu ...

Page 197: ... press Y key to confirm exit 6 5 iSCSI Boot BIOS supports iSCSI boot in UEFI mode from Front Panel Ethernet Base Ethernet and Fabric Ethernet The following chapter describes the iSCSI configuration menu Ensure that in the BIOS Setup in the Boot Menu the Boot Type is set to Dual Boot Type or UEFI Boot Type and the PXE Boot capability is set to UEFI IPv4 Steps to configure iSCSI boot 1 Enter the Boo...

Page 198: ...Configuration Menu Item Values IPMI Boot parameter Description ISCSI Initiator Name The worldwide unique name of the iSCSI Initiator Only IQN format is accepted Add Attempt Add an iSCSI Attempt Delete Attempts Delete an iSCSI Attempt Change Attempt Order Change the order of iSCSI Attempts ...

Page 199: ...BIOS ATCA 7490 Installation and Use 6806800U11F 199 Add an ISCSI Attempt ...

Page 200: ...connect using the IPv6 stack Connection Retry Count The count range is 0 to 16 Ifsetto0 thereareno retries 0 40 The minimum value is 0 and the maximum is 40 0 means no retry It will stall 1 second and reconnect Connection Establishing Timeout 100 20000 The timeout value in milliseconds The minimum value is 100 milliseconds and the maximum is 20 seconds Configure ISID Derived from the MAC address T...

Page 201: ... set the hexadecimal representationofthebootlogical unit number LUN Example 4752 3A4F 6b7e 2F99 Authentication Type CHAP None Define the Challenge Handshake Authentication Protocol CHAP Available settings are CHAP Kerberos and None CHAP Type One Way Mutual Use to set CHAP type to either One Way or Mutual CHAP Name Set the CHAP name CHAP Secret Use to set the CHAP secret password The secret length ...

Page 202: ...s are loaded when selecting the Restore Defaults Item on BIOS Save and Exit Menu A detailed description of the IPMI Boot Parameter and the corresponding IPMI commands is available in System Boot Options Parameter 100 on page 265 The main advantage of using IPMI boot parameter is that the parameters stored as IPMI boot parameters are not changed after a BIOS upgrade or a BIOS boot bank switch BIOS ...

Page 203: ...or Save and Exit option 3 BIOS writes the parameter to the BIOS Parameter in the Flash 4 BIOS writes the parameter to the IPMI Boot Parameter USER area Load Defaults 1 User enters BIOS setup and selects Load Defaults 2 BIOS reads Default Parameter from Flash into the Setup 3 BIOS reads IPMI Boot Parameter DEFAULT area into the Setup 4 User selects Save or Save and Exit option 5 BIOS writes the par...

Page 204: ...ows the Main menu options Figure 6 11 Main Menu Options Table 6 3 Main Menu Item Values IPMI Boot parameter Description System Time 15 48 21 Set the Time Use Enter to switch between Time elements System Date Thu 11 11 2014 Set the Date Use Enter to switch between Date elements ...

Page 205: ...BIOS ATCA 7490 Installation and Use 6806800U11F 205 6 7 2 Advanced Platform Information This option shows important information about Platform CPU QPI and Memory Figure 6 12 Platform Information ...

Page 206: ...guration Table 6 4 Advanced RTM Configuration Item Values IPMI Boot parameter Description Auto Detect RTM Enabled Disabled rtm_auto If enabled the RTM is detected and the RTM PCI Express parameter are set for this RTM If disabled the RTM PCI Express parameter can be set manually CPU0 PCIe to RTM Width X4x4x4x4 x4x4x8 x8x4x4 x8x8 rtm_cpu0_bif Selects CPU0 PCIe Bifurcation for Zone3connector RTM ...

Page 207: ... Zone 3 connector RTM CPU0 PCIe Port 3C Auto Gen 1 2 5 GT s Gen 2 5 GT s Gen 3 8 GT s rtm_cpu0_3c Selects CPU0 PCIe Port 3C Speed for Zone 3 connector RTM CPU0 PCIe Port 3D Auto Gen 1 2 5 GT s Gen 2 5 GT s Gen 3 8 GT s rtm_cpu0_3d Selects CPU0 PCIe Port 3D Speed for Zone 3 connector RTM CPU1 PCIe to RTM Width X4x4x4x4 x4x4x8 x8x4x4 x8x8 rtm_cpu1_bif Selects CPU1 PCIe Bifurcation for Zone 3 connect...

Page 208: ...Gen 3 8 GT s rtm_cpu1_3b Selects CPU1 PCIe Port 3B Speed for Zone 3 connector RTM CPU1 PCIe Port 3C Auto Gen 1 2 5 GT s Gen 2 5 GT s Gen 3 8 GT s rtm_cpu1_3c Selects CPU1 PCIe Port 3C Speed for Zone 3 connector RTM CPU1 PCIe Port 3D Auto Gen 1 2 5 GT s Gen 2 5 GT s Gen 3 8 GT s rtm_cpu1_3d Selects CPU1 PCIe Port 3D Speed for Zone 3 connector RTM Table 6 4 Advanced RTM Configuration continued Item ...

Page 209: ...ipheral Configuration Item Values IPMI Boot parameter Description Front Panel Ethernet Enabled Disabled frontnet Enables Disables Front Panel Ethernet PCIe SR IOV Support Enabled Disabled pci_sriov Enables Disables PCI Express Single Root I O Virtualization PCIe ARI Enabled Disabled pci_ari Enables Disables Alternative Routing ID Interpretation ARI Pci 64 bit Decode Enabled Disabled pci_64bit Allo...

Page 210: ...hernet Figure 6 15 Peripheral Intel VT Configuration Table 6 6 Advanced Peripheral Configuration Intel VT for Directed I O VT d Item Values IPMI Boot parameter Description VTd Azalia VCp Optimizations Enabled Disabled Enables Disables virtualization optimizations for Azalia Table 6 5 Advanced Peripheral Configuration continued Item Values IPMI Boot parameter Description ...

Page 211: ...ugh DMAR ACPI Tables Interrupt Remapping Enabled Disabled vtd_ir Enables Disables VT_D Interrupt Remapping support Coherency Support Non Isoch Enabled Disabled Enables Disables non isochronous coherency support Coherency Support Isoch Enabled Disabled Enables Disables isochronous coherency support Table 6 6 Advanced Peripheral Configuration Intel VT for Directed I O VT d continued Item Values IPMI...

Page 212: ...iguration Figure 6 16 SATA Configuration Table 6 7 Advanced SATA Configuration Item Values IPMI Boot parameter Description SATA Controller Enabled Disabled sata Enables Disables SATA Device Operation Mode IDE AHCI RAID sata_mode Selects the controllers Operation Mode RAID OROM prompt delay 2 4 6 8 Seconds sata_raidwait Time for delay of SATA RAID Option ROM prompt ...

Page 213: ...es Disables Aggressive Link Power Management SALP SATA Speed Support 1 5 Gb s 3 0 Gb s 6 0 Gb s sata_speed Indicates the maximum speed theSATAcontrollercansupport on its ports Only usable in AHCI RAID mode Figure 6 17 USB Configuration Table 6 7 Advanced SATA Configuration continued Item Values IPMI Boot parameter Description ...

Page 214: ...se storage support under UEFI and DOS environment If UEFI Only is set it supports only in UEFI environment USB1 Front Panel Enabled Disabled usb1 Enables Disables USB Front Panel Port 1 USB2 Front Panel Enabled Disabled usb2 Enables Disables USB Front Panel Port 2 USB to RTM Enabled Disabled usb_rtm Enables Disables USB to RTM USB1 3 0 Front Panel Enabled Disabled usb1_3 Enables Disables USB1 Fron...

Page 215: ...ssor Configuration Table 6 9 Advanced Processor Configuration Item Values IPMI Boot parameter Description Socket 0 Core Disable 0 to 3FFE cpu0_dism Core Disable Bitmap Hex Value 0 Enable all cores Valid Range 0 to 3FFE 3FFF Disabling all cores Invalid Socket 1 Core Disable 0 to 3FFE cpu1_dism Core Disable Bitmap Hex Value 0 Enable all cores Valid Range 0 to 3FFE 3FFF Disabling all cores Invalid ...

Page 216: ...o improve the virtualization performance and robustness Hardware Prefetcher Enabled Disabled cpu_hp Enables Disables the hardware prefetcher Adjacent Cache Prefetch Enabled Disabled cpu_acp When enabled optimizes the system for applications that require high utilization of sequential memory access When disabled optimizes the system for applications that require high utilization of random memory ac...

Page 217: ...ration Figure 6 19 Processor Power Management Configuration Table 6 10 Advanced Processor Configuration Processor Power Management Configuration Item Values IPMI Boot parameter Description Enhanced Intel SpeedStep Enabled Disabled cpu_ss Enables Disables Enhanced Intel SpeedStep Technology P States Turbo Mode Enabled Disabled cpu_tm Enables Disables processor Turbo Mode ...

Page 218: ...ate C6 non Retention state C6 Retention state No Limit cpu_cslimit Specifies the lowest C state for the package Higher C States will save more power Lower C States will have lower wake up latencies CPU C3 report Enabled Disabled cpu_c3 Enables Disables CPU C3 ACPI C3 report to OS CPU C6 report Enabled Disabled cpu_c6 Enables Disables CPU C6 ACPI C3 report to OS Enhanced Halt State C1E Enabled Disa...

Page 219: ...gure 6 20 Memory Configuration Table 6 11 Advanced Memory Configuration Item Values IPMI Boot parameter Description Memory Frequency Auto 1333 1600 1867 2133 mem_speed MaximumMemoryFrequency Selections in MHz Halt on Training Error Enabled Disabled mem_halt Enables Disables Halt on Memory Training Error NUMA Enabled Disabled mem_numa Enables Disables Non Uniform Memory Access NUMA ...

Page 220: ...Long mem_test Select Hardware Memory Test Rank Margin Tool Enabled Disabled mem_rmt Enable Disable memory Rank Margin Tool which tests the DRAM signal margins Figure 6 21 Memory RAS Configuration Table 6 11 Advanced Memory Configuration continued Item Values IPMI Boot parameter Description ...

Page 221: ... Item Values IPMI Boot parameter Description RAS Mode Disable Mirror Lockstep Mode mem_ras Enables Disables RAS modes Enabling Sparing and Mirroring is not supported Incase if enabled Sparing will be selected Memory Rank Sparing Enabled Disabled mem_sparing Enables Disables Memory Rank Sparing Patrol Scrub Enabled Disabled mem_ps Enables Disables Patrol Scrub Demand Scrub Enabled Disabled mem_ds E...

Page 222: ...ction Figure 6 22 Console Redirection Table 6 13 Advanced Console Redirection Item Values IPMI Boot parameter Description TerminalType VT_100 VT_100 VT_UTF8 PC_ANSI con_tt Sets Console Redirection terminal type Baud Rate 115200 57600 38400 19200 9600 4800 2400 1200 con_br Sets Console Redirection baud rate Data Bits 7 Bits 8 Bits con_db Sets Console Redirection data bits ...

Page 223: ...ts 1 Bit 2 Bits con_sb Sets Console Redirection stop bits Flow Control None XON XOFF con_fc Sets Console Redirection flow control type C R After Post Yes No con_ap Continue Console Redirection after POST when OS is loaded Figure 6 23 APEI Configuration Table 6 13 Advanced Console Redirection continued Item Values IPMI Boot parameter Description ...

Page 224: ...ei Disables Enables ACPI Platform Error Interface APEI and Windows Hardware Error Architecture WHEA AEPI extends hardware error reporting mechanisms and brings them together as components of a coherent hardware error infrastructure APEI Error Injection Disabled MEMORY_CE MEMORY_UE_NON_ FATAL MEMORY_UE_FATAL PCIE_CE PCIE_UE_NON_FATAL PCIE_UE_FATAL Inject an error to test APEI feature APEI UEFI Revi...

Page 225: ...BIOS ATCA 7490 Installation and Use 6806800U11F 225 BIOS Event Log Configuration For more information refer to BIOS Error Logging on page 239 Figure 6 24 BIOS Event Log Configuration ...

Page 226: ...BIOS ATCA 7490 Installation and Use 6806800U11F 226 Figure 6 25 Event Log Viewer ...

Page 227: ...scription about the options on Memory Event Log Viewer screen Figure 6 26 Memory Event Log Viewer Table 6 15 Advanced Memory Event Log Viewer Item Description Clear Memory Event Log Clears the BIOS stored event log Clear BMC SEL Event Log Clears the SEL in the IPMC called as BMC here ...

Page 228: ... about the options that can be configured in IPMI configuration Figure 6 27 IPMI Configuration Table 6 16 Advanced IPMI Configuration Item Values IPMI Boot parameter Description IPMI KCS Interrupt Enabled Disabled ipmi_irq Enables Disables usage of Host Interface KCS interrupt KCS interrupt is hardwired to IRQ 6 ...

Page 229: ...wd_action Configure how the system should respond if the OS Boot Watchdog Timer expires IPMI Fail Safe Enabled Disabled No Change failsafe Enables Disables Fail Safe Policy Enabled IPMC will switch the BIOS boot bank if the FRB2 watchdog expires No Change Fail Safe Policy will not be changed by BIOS Show Sensor Data Shows Sensor Data Records SDR Lists all SDR information provided by the IPMC Execu...

Page 230: ...e contains information about the options available for Security configuration Figure 6 28 Security Table 6 17 Security Item Values IPMI Boot parameter Description TPM Operation No Operation Disable and Deactivate Enable and Activate tpm_operation Enables Disables TPM Function This option will automatically return to No Operation ...

Page 231: ...6 7 4 Boot Figure 6 29 shows the Boot menu options SetSupervisor Password Install or Change the password The length of password must be greater than one character Table 6 17 Security continued Item Values IPMI Boot parameter Description Figure 6 29 Boot ...

Page 232: ..._netprot Disabled Support Network Stack UEFI PXE IPv4 IPv6 Legacy Legacy PXEOPROM only Front Panel Net Boot Enabled Disabled boot_frontnet Controls execution of the Option ROM for the Front Panel Ethernet controller Select Enabled when Front Panel Boot is required Base Network Boot Enabled Disabled boot_basenet Controls execution of the Option ROM for both Base Network Ethernet controller Select E...

Page 233: ...s to configure the order of the EFI Boot devices Use the Up and Down keys to select a device Use and keys to move the devices up or down With the key a boot device can be enabled or disabled If the boot entry shows as first character this boot entry is disabled Figure 6 30 EFI Boot Order ...

Page 234: ...ws configuring the order of the Legacy Boot Use the Up and Down keys to select a device Use and keys to move the devices up or down With the key a boot device can be enabled or disabled If the boot entry shows as first character this boot entry is disabled Figure 6 31 Legacy Boot Order ...

Page 235: ...e options available in Exit menu Figure 6 32 Exit Menu Table 6 19 Exit Item Values IPMI Boot parameter Description Exit Saving Changes Saves the changes made and then exits the system Save Change Without Exit Saves the changes without exiting the system Exit Discarding Changes Exitsthesystemwithoutsavingthe changes Load Defaults Loads default Settings ...

Page 236: ...her Boot Type in Boot Menu is set to Dual Boot Type or UEFI Boot Type 2 Press F4 key during boot process to enter Boot menu 3 In the Boot menu select the Administer Secure Boot and press Enter BIOS restarts the board and enter the Administer Secure Boot menu automatically Discard Changes Discards the changes Table 6 19 Exit continued Item Values IPMI Boot parameter Description ...

Page 237: ...n board configuration switch that allows to load BIOS settings from the DEFAULT area of the IPMI Boot Parameters In order to restore the BIOS default settings using this switch 1 Remove the blade from the system 2 Set the on board switch SW3 4 to ON See Switch Settings on page 53 for the exact location of SW3 3 Install and power up the blade 4 Wait until the blade has completely booted and is up a...

Page 238: ...ot error in case of no boot device found Reads IPMI GUID and fills in the DMI structure 1 UUID Shows SEL and Sensors in BIOS setup Creates the DMI structure type 38 to provide IPMI host interface information to the OS Reads and creates the IPMI boot parameters which are stored in the IPMC 6 11 Watchdog Support BIOS uses the IPMI payload watchdog for two phases BIOS phase Operation System boot phas...

Page 239: ...ration Event Log Viewer Enter Event Log Viewer You can select either Memory Event Log Viewer or BMC SEL Event Log Viewer options here to view their respective details Errors are logged to the IPMI controller Table 6 20 Logged Error Events Error IPMI Correctable Correctable ECC Memory Error Sensor Memory Offset 00h Correctable Memory Error Limit Reached CorrectableECClogginglimitreached Sensor Memo...

Page 240: ...uilt In Self Test BIST Error 30h Exception Divide Error 31h Exception Invalid Opcode 32h Exception Stack Fault 33h Exception GP Fault 34h Exception Math Error 35h Exception Alignment Check 36h Exception Machine Check 50h IPMI Boot Parameter Default Area Read Error 51h IPMI Boot Parameter Default Area Locked 52h IPMI Boot Parameter Default Area Checksum Error 53h IPMI Boot Parameter User Area Read ...

Page 241: ... initialization 04h User authentication 05h User initiated system setup 06h USB configuration 07h PCI configuration 08h Option ROM initialization 09h Video initialization 0Ah Cache initialization 0Ch Console input initialization 13h Starting Operating System FDh OEM Error Extension Supported Event Data3 FDh OEM Error Extension 90h Reboot after a FRB2 Watchdog Timeout 91h Reboot after a BIOS POST W...

Page 242: ...Offset 00h Correctable ECC Offset 01h Uncorrectable ECC Offset 04h Memory Device Disabled Offset 05h Correctable ECC error logging limit reached Offset 06h Presence detected Event Data2 0xFF Event Data3 Bit Description 0 3 Sequential DIMM number 1 to 8 4 7 CPU Socket 1 to 2 See Figure ATCA 7490 Blade Layout on page 52 for DIMM naming convention Critical Interrupt 13h Offset 04h PCI PERR Offset 05h...

Page 243: ... Upgrade on page 313 6 15 BIOS POST Codes The following table lists the BIOS POST codes The BIOS POST codes are written to the blade s I O Port 80 register and can be obtained by reading the POST code on board IPMI sensor The reading of the POST code sensor is only valid when the board is in the BIOS phase The reading can be used to locate the cause of a board hang during BIOS phase When the board...

Page 244: ...processor Early Initial 73h HyperTransport Initial 74h PCIE MMIO BAR Initial 75h North Bridge Early Initial 76h South Bridge Early Initial 77h PCIE Training 78h TPM Initial 79h SMBUS Early Initial 7Ah Clock Generator Initial 7Bh Internal Graphic device early initial PEI_IGDOpRegion 7Ch HECI Initial 7Dh Watchdog timer initial 7Eh Memory Initial for Normal boot 7Fh Memory Initial for Crisis Recovery...

Page 245: ...initial in DXE 41h South bridge SPI initial 42h Setup Reset service DXE_CF9Reset 43h South bridge Serial GPIO initial DXE_SB_SerialGPIO_INIT 44h Setup SMM ACCESS service 45h North bridge Middle initial 46h Super I O DXE initial 47h Setup Legacy Region service DXE_LegacyRegion 48h South Bridge Middle Initial 49h Identify Flash device 4Ah Fault Tolerant Write verification 4Bh Variable Service Initia...

Page 246: ...al 5Bh ACPI Table Initial 5Ch Setup SB SMM Dispatcher service DXE_SB_Dispatch 5Dh Setup SB IOTRAP Service 5Eh Build AMT Table 5Fh PPM Initial 60h HECIDRV Initial 61h Variable store garbage collection and reclaim operation 62h Do not support flash part which is defined in SpiDevice c 10h Enter BDS entry 11h Install Hotkey service 12h ASF Initial 13h PCI enumeration 14h PCI resource assign complete ...

Page 247: ...22h Floppy device initial 23h Serial device initial 24h IDE device initial 25h AHCI device initial 26h Dispatch option ROMs 27h Get boot device information 28h End of boot selection 29h Enter Setup Menu 2Ah Enter Boot manager 2Bh Try to boot system to OS 2Ch Shadow Misc Option ROM 2Dh Save S3 resume required data in RAM 2Eh Last Chipset initial before boot to OS 2Fh Start to boot Legacy OS 30h Sta...

Page 248: ...dentify Flash device in SMM A2h SMM service initial A6h OS call ACPI enable function A7h ACPI enable function complete A1h Enter S1 A3h Enter S3 A4h Enter S4 A5h Enter S5 A8h OS call ACPI disable function A9h ACPI disable function complete C0h Memory initial for S3 resume C1h Get S3 resume required data from memory C2h Start to use memory during S3 resume C3h Set cache for physical memory during S...

Page 249: ...on Collect info such as SBSP Boot Mode Reset type and so on A2h QPI Initialization Setup IO SADs in SBSP to access the config space A3h QPI Initialization Setup up minimum path between SBSP other sockets A4h QPI Initialization Setup IO SADs in PBSP to access the config space A5h QPI Initialization System configurations that require some kind of reset A6h QPI Initialization Sync up with PBSPs A7h Q...

Page 250: ...3h Memory Initialization Early Init B4h Memory Initialization Rank Detection B5h Memory Initialization Early Channel Init B6h Memory Initialization JEDEC Init B7h Memory Initialization Channel Training B8h Memory Initialization Throttling Init B9h Memory Initialization BIST BAh Memory Initialization Init BBh Memory Initialization DDR Memory Mapping BCh Memory Initialization RAS Configuration BDh M...

Page 251: ...used to transmit receive its terminal characters via base interface 7 1 Configuring SOL Parameters You can configure the SOL parameters via standard IPMI commands or via an open source tool called ipmitool The ATCA 7490 supports two SOL channels which are available at their base interfaces However only one SOL session is allowed at a time Figure 7 1 SOL Overview Faceplate FPGA IPMC CPU Intel NIC S...

Page 252: ...l IPMC and the IP is configured The ipmicmd is part of the open IPMI package provided in BBS For more details about BBS refer to Basic Blade Services Software on ATCA 7490 Programmer s Reference manual Sample Procedure To set the IP address 1 Establish an IPMI connection to the blade 2 Set LAN Configuration Parameter Set In Progress Lock ipmicmd k f 0 c 1 1 0 1 smi 0 3 Set LAN Configuration Parame...

Page 253: ... same procedure can be used to configure channel 2 7 1 2 Configuration using ipmitool 7 1 2 1 Installing the ipmitool Youcandownloadtheopensourcetoolipmitoolfromhttp ipmitool sourceforge net atthe timeofpublishingthismanualthecurrentversionis1 8 13 Documentationforthistoolisalso freely available on this site Procedure To install the ipmitool 1 Download the ipmitool tar file from http ipmitool sour...

Page 254: ...0 221 Setting LAN IP Address to 172 16 0 221 To set the ip address of channel 1 from shelf external host prompt ipmitool I lan H Shelf Manager_IP U Shelf User_Name P Shelf Password b 0 t ipmb_addr_of_target_board lan set 1 ipaddr 172 16 0 221 Setting LAN IP Address to 172 16 0 221 In this section all other parameters will be sent from Linux running on the board itself root ATCA7490 ipmitool lan se...

Page 255: ...P Address Source Unspecified IP Address 172 16 0 221 Subnet Mask 255 255 0 0 MAC Address ec 9e cd 10 a0 64 Default Gateway IP 172 16 0 1 Default Gateway MAC 00 00 00 00 00 00 RMCP Cipher Suites 1 2 3 3 Cipher Suite Priv Max Not Available root ATCA7490 ipmitool lan print 2 Set in Progress Set Complete Auth Type Support Auth Type Enable Callback User Operator Admin OEM ...

Page 256: ...ance the default baud rate is 115200 The default user name is soluser and default user password is solpasswd This example below shows how to query sol parametercurrentlyinuseforapotentialSOLsessionforbase1 channel1 andbase2 channel 2 root ATCA7490 ipmitool sol info 1 Info SOL parameter Payload Channel 7 not supported defaulting to 0x01 Set in progress set complete Enabled true Force Encryption fal...

Page 257: ...info 2 Info SOL parameter Payload Channel 7 not supported defaulting to 0x02 Set in progress set complete Enabled true Force Encryption false Force Authentication false Privilege Level ADMINISTRATOR Character Accumulate Level ms 5 Character Send Threshold 1 Retry Count 1 Retry Interval ms 50 Volatile Bit Rate kbps 115 2 Non Volatile Bit Rate kbps 115 2 Payload Channel 2 0x02 Payload Port 623 ...

Page 258: ...e network between the ATCA 7490 and your target which is destined for opening the SOL session so that the SOL IP address is accessible 5 Start ATCA 7490 SOL session on your target with the ipmitool and the configured IP address for the ATCA 7490 SOL interface ipmitool C 1 I lanplus H 172 16 0 221 U soluser P solpasswd k gkey sol activate For more details on the command parameters refer to the ipmi...

Page 259: ...ing global IPMI commands 8 1 2 System Interface Commands The system interface commands are supported by blades providing a system interface Table 8 1 Supported Global IPMI Commands Command NetFn Request Response CMD Comments Get Device ID 0x06 0x07 0x01 Cold Reset 0x06 0x07 0x02 Warm Reset 0x06 0x07 0x03 Get Self Test Results 0x06 0x07 0x04 Get Device GUID 0x06 0x07 0x08 Master Write Read 0x06 0x0...

Page 260: ...7 0x41 Get Channel Info 0x06 0x07 0x42 Set User Access 0x06 0x07 0x43 Get User Access 0x06 0x07 0x44 Set User Name 0x06 0x07 0x45 Get User Name 0x06 0x07 0x46 Set User Password 0x06 0x07 0x47 Set User Payload Access 0x06 0x07 0x4C Get User Payload Access 0x06 0x07 0x4D Set Channel Security Keys 0x06 0x07 0x5C Table 8 2 Supported System Interface Commands continued Command NetFn Request Response CM...

Page 261: ...y commands Table 8 4 Supported SEL Device Commands Command NetFn Request Response CMD Get SEL Info 0x0A 0x0B 0x40 Reserve SEL 0x0A 0x0B 0x42 Get SEL Entry 0x0A 0x0B 0x43 Add SEL Entry 0x0A 0x0B 0x44 Clear SEL 0x0A 0x0B 0x47 Get SEL Time 0x0A 0x0B 0x48 Set SEL Time 0x0A 0x0B 0x49 Table 8 5 Supported FRU Inventory Commands Command NetFn Request Response CMD Get FRU Inventory Area Info 0x0A 0x0B 0x10...

Page 262: ...4 0x05 0x23 Set Sensor Hysteresis 0x04 0x05 0x24 Get Sensor Hysteresis 0x04 0x05 0x25 Set Sensor Threshold 0x04 0x05 0x26 Most of the threshold based sensors have fixed thresholds Before using this command check whether threshold setting is supported by using the Get Device SDR command Get Sensor Threshold 0x04 0x05 0x27 Set Sensor Event Enable 0x04 0x05 0x28 Get Sensor Event Enable 0x04 0x05 0x29...

Page 263: ... OEM specific which can be used for different purposes When using the Get Set System Boot Options commands except for parameter 100 use the response request data fields with the Set Selector and the Block Selector set to 0x00 When using the Get Set System Boot Option for the parameter 100 the Set Selector and the Block Selector have a specific meaning For more details see System Boot Options Param...

Page 264: ...ion 1 Bits 7 2 Reserved Bit 1 FPGA configuration stream load 0 Load configuration stream from default boot flash 1 Load configuration stream from backup boot flash Note ThenewFPGAconfigurationstreamisloadedintotheFPGAatthenextpower up of the payload Bit 0 Default backup boot flash selection 0 Boot from default boot flash 1 Boot from backup boot flash Note Thenewlyselectedbootflashisconnectedtothep...

Page 265: ...oot firmware directly for example using a Setup menu The IPMC contains a storage area where the boot parameters are stored When the blade boots the boot firmware reads out the storage area interprets the parameters and executes the boot process accordingly Table 8 10 System Boot Options Parameter 98 Bit Description 15 8 Timeout for GRACEFUL_SHUTDOWN LSB given in 100 msec 7 0 Timeout for GRACEFUL_S...

Page 266: ...hus use the factory settings you need to configure the blade accordingly This is typically done by an on board switch for example Clear CMOS RAM It depends on the blade and firmware which settings are stored in the default area The details are given in the following sections The following figure summarizes the previously explained basic information flow related to the system boot options parameter...

Page 267: ...rmat Byte Description 0 1 Number of bytes used for boot parameters LSB first The number of bytes must be calculated and written into these two bytes by the software which writes into the storage area The values 0x0000 and 0xFFFF indicate that no data has been written to the storage area When reading from the storage area and you find any of these two values your software should assume that no user...

Page 268: ... option data your software may need to write several blocks of 16 bytes in a row each individually addressed using the block selector 4 n n 19 Data that you want to write into the addressed block This will be a chunk of the boot parameter data If less than 16 bytes are written then only the provided data is written the remaining bytes in the addressed storage area block are left unchanged Response...

Page 269: ...e area is locked Bits 6 0 value 100 indicating this OEM boot option command 4 19 The content of the read 16 byte block Table 8 13 System Boot Options Parameter 100 GET Command Usage continued Byte Description In order to detect the maximum size of writable storage area your software can perform a series of read accesses while incrementing the block selector with each access Once the error code C9 ...

Page 270: ... RTM PCIe parameter can be set manually on off rtm_cpu0_bif Selects CPU0 PCIe Bifurcation for Zone 3 connector RTM X4x4x4x4 x4x4x8 x8x4x4 x8x8 rtm_cpu0_3a Selects CPU0 PCIe Port 3A Speed for Zone 3 connector RTM auto gen1 gen2 gen3 rtm_cpu0_3b Selects CPU0 PCIe Port 3B Speed for Zone 3 connector RTM auto gen1 gen2 gen3 rtm_cpu0_3c Selects CPU0 PCIe Port 3C Speed for Zone 3 connector RTM auto gen1 ...

Page 271: ...Selects CPU1 PCIe Port 3D Speed for Zone 3 connector RTM auto gen1 gen2 gen3 frontnet Enable Disable Front Panel Ethernet on off pci_sriov PCI Express Single Root I O Virtualization on off pci_ari Alternative Routing ID nterpretation ARI on off pci_64bit 64 bit BAR support for PCI devices on off clock_ssc Spread Spectrum Clock on off vtd Intel Virtualization Technology for Directed I O VT d on off...

Page 272: ...A speed 1 5 3 6 usb USB Support on off uefi usb1 Enable Disable USB Front Panel Port 1 on off usb2 Enable Disable USB Front Panel Port 2 on off usb_rtm Enable Disable USB to RTM on off usb1_3 USB1 Front Panel USB 3 0 support on off usb2_3 USB2 Front Panel USB 3 0 support on off cpu0_dism Core Disable Bitmap Hex Value 0 Enable all cores Valid Range 0 to 3FFE 3FFF Disabling all cores Invalid Hex Val...

Page 273: ...hnology TXT on off cpu_vt CPU Virtualization VT x on off cpu_hp CPU Hardware Prefetcher on off cpu_acp CPU Adjacent Cache Prefetcher on off cpu_dca CPU Direct Cache Access DCA on off cpu_x2apic CPU Extended APIC support on off cpu_ss CPU Enhanced Intel SpeedStep Technology P States on off cpu_tm CPU Turbo Mode on off cpu_ppw Turbo Mode Performance Watt tradi optim cpu_cstates CPU C State support o...

Page 274: ...f cpu_cxacpi Report ACPI Cx State c2 c3 mem_speed Memory Frequency MHz auto 1333 1600 1867 2133 mem_halt Halt on Training Error on off mem_numa Disable Non Uniform Memory Access NUMA on off mem_test Hardware Memory Test off short long mem_ras Memory RAS modes off mirror lockstep mem_sparing Memory Rank Sparing on off Table 8 14 System Boot Options Parameter 100 Supported Parameters continued Param...

Page 275: ...vt100 utf8 ansi con_br Serial console baud rate 9600 19200 38400 57600 115200 con_db Serial console data bits 7 8 con_par Serial console parity bits o e o con_sb Serial console stop bits 1 2 con_fc Serial console flow control off hard soft con_ap Serial console redirection after POST on off apei APEI Support on off Table 8 14 System Boot Options Parameter 100 Supported Parameters continued Paramet...

Page 276: ...t_wd_action 0S Watchdog Timeout Action noaction reset poweroff powercycle failsafe IPMI Fail Safe on off nochange tpm_operation TPM Function This option will automatically return to No Operation no_operation disable_deactivate enable_activate boot_type Boot Type dual legacy uefi boot_priority Determine whether EFI devices or Legacy devices are booted first uefi legacy Table 8 14 System Boot Option...

Page 277: ...der Set the Boot Order See Table 8 15 device1 deviceN separated by comma Table 8 15 Boot Order Devices Boot Device Description sata0 Onboard SATA device P1 sata1 Onboard SATA device P2 sata2 Onboard SATA device P3 sata3 SATA device RTM raid0 SATA RAID device 0 raid1 SATA RAID device 0 raid2 SATA RAID device 0 raid3 SATA RAID device 0 frontnet1 Front Panel Network 1 frontnet2 Front Panel Network 2 ...

Page 278: ...Pv4 efifrontnet2 EFI Front Panel Network 2 IPv4 efibasenet1 EFI Base Network 1 IPv4 efibasenet2 EFI Base Network 2 IPv4 eiffrontnet1v6 EFI Front Panel Network 1 IPv6 efifrontnet2v6 EFI Front Panel Network 2 IPv6 efibasenet1v6 EFI Base Network 1 IPv6 efibasenet2v6 EFI Base Network 2 IPv6 efiusb EFI Boot from USB device efiusb1 EFI Boot from USB device connected to USB1 efiusb2 EFI Boot from USB dev...

Page 279: ...ds information vmware VMware Table 8 15 Boot Order Devices continued Boot Device Description Table 8 16 Supported LAN Device Commands Command NetFn Request Response CMD Set LAN Configuration Parameters 0x0C 0x0D 0x01 Get LAN Configuration Parameters 0x0C 0x0D 0x02 Set SOL Configuration Parameters 0x0C 0x0D 0x21 Get SOL Configuration Parameters 0x0C 0x0D 0x22 Table 8 17 Supported PICMG 3 0 Commands...

Page 280: ...Set Port State 0x2C 0x2D 0x0E Get Port State 0x2C 0x2D 0x0F Compute Power Properties 0x2C 0x2D 0x10 Set Power Level 0x2C 0x2D 0x11 Get Power Level 0x2C 0x2D 0x12 Get IPMB Link Info 0x2C 0x2D 0x18 Set AMC Port State 0x2C 0x2D 0x19 Get AMC Port State 0x2C 0x2D 0x1A Get FRU Control Capabilities 0x2C 0x2D 0x1E Get target upgrade capabilities 0x2C 0x2D 0x2E Get component properties 0x2C 0x2D 0x2F Abort...

Page 281: ... 17 Supported PICMG 3 0 Commands continued Command NetFn Request Response CMD Comments The firmware upgrade commands supported by the blade are implemented according to the PICMG HPM 1 Revision 1 0 specification The boot block can be updated with PICMG HPM 1 specific commands Before sending any of these commands the shelf management software must check whether the receiving IPMI controller support...

Page 282: ...e 282 Get Serial Output 0x2E 0x2F 0x16 See Get Serial Output Command on page 283 Table 8 19 Request Data of Set Serial Output Command Byte Data Field 1 LSB of Artesyn IANA Enterprise number A value of 0xCD has to be used 2 Second byte of Artesyn Embedded Technologies IANA Enterprise number A value of 0x65 has to be used 3 MSB of Artesyn Embedded Technologies IANA Enterprise number A value of 0x00 ...

Page 283: ...articular serial port connector 6 Serial output selector 0 BIOS 2 IPMC debug console All other values are reserved Table 8 19 Request Data of Set Serial Output Command continued Byte Data Field Table 8 20 Response Data of Set Serial Output Command Byte Data Field 1 Completion code 2 LSB of Artesyn Embedded Technologies IANA Enterprise number 3 Second byte of Artesyn Embedded Technologies IANA Ente...

Page 284: ...cond byte of Artesyn IANA Enterprise number A value of 0x65 has to be used 3 MSB of Artesyn IANA Enterprise number A value of 0x00 has to be used 4 Serial connector type 0 Faceplate connector 1 Backplane connector All other values are reserved Note Only the faceplate connector is supported No connector on the RTM available 5 Serial connector instance number A sequential number that starts from 0 T...

Page 285: ... provides information about the OEM command to configure IPMI features Table 8 23 Feature Configuration Command Command NetFn Request Response CMD Defined in Set Feature Configuration 0x2E 0x2F 1Eh Set Feature Configuration Command on page 286 Get Feature Configuration 0x2E 0x2F 1Fh Get Feature Configuration Command on page 287 ...

Page 286: ...s see Table 8 25 5 Feature Configuration Bit 7 0 Feature Selector E0h E1h 00h disabled 01h enabled 02h 0ffh reserved Bit 7 0 Feature Selector 03h 00h FFh Debounce timer timeout value in 100ms 6 Persistency Duration 00h volatile Actual duration depends on implementation 01h FFh reserved Response Data 1 Completion Code Generic plus the following command specific completion codes 80h feature selector...

Page 287: ...elector Description 3 03h Handle Debounce 224 E0h FAILSAFE Function Enable Disable For details see Fail Safe Logic on page 349 225 E1h FAIL PROTECT Function Enable Disable For details see Fail Protect Logic on page 352 Table 8 26 Get Feature Configuration Command Byte Data Field Request Data 1 LSBofArtesynIANAEnterpriseNumber AvalueofCDhshallbe used 2 2nd byte of Artesyn IANA Enterprise Number A v...

Page 288: ...MSB of Artesyn IANA Enterprise Number A value of 00h shall be used 5 Feature Configuration Bit 7 0 Feature Selector E0h E1h 00h disabled 01h enabled 02h 0ffh reserved Bit 7 0 Feature Selector 03h 00h FFh Debounce timer timeout value in 100 ms 6 Persistency Duration Table 8 26 Get Feature Configuration Command continued Byte Data Field Table 8 27 Pigeon Point Extension Commands Command NetFn Reques...

Page 289: ...302 0x2E 0x2F 0x0B Disable Payload Control Table 8 42 on page 302 0x2E 0x2F 0x0C Reset IPMC Table 8 30 on page 292 0x2E 0x2F 0x0D Hang IPMC Table 8 43 on page 303 0x2E 0x2F 0x0E Graceful Reset Table 8 44 on page 303 0x2E 0x2F 0x11 Get Payload Shutdown Time Out Table 8 45 on page 304 0x2E 0x2F 0x15 Set Payload Shutdown Time Out Table 8 46 on page 305 0x2E 0x2F 0x16 Get Module State Table 8 47 on pa...

Page 290: ...is intended for debugging purposes and or operation in a non ATCA environment In standalone mode the carrier IPMC automatically activates and deactivates the on carrier payload and modules whenever it does not violate any carrier limitations Manual standalone Manual standalone mode is equivalent to standalone mode with only one exception carrier IPMC control over the on carrier payload is automati...

Page 291: ... threshold crossing Bits 2 1 Mode The current IPMC modes are defined as 0 Normal 1 Standalone for a description refer to Table 8 28 2 Manual Standalone for a description refer to Table 8 28 Bit 0 Control If set to 0 the IPMC control over the payload is disabled 6 Bits 4 7 Metallic Bus 2 Events These bits indicate pending Metallic Bus 2 requests arrived from the shelf manager 0 Metallic Bus 2 Query...

Page 292: ...cate pending Clock Bus 1 requests arrived from the shelf manager 0 Clock Bus 1 Query 1 Clock Bus 1 Release 2 Clock Bus 1 Force 3 Clock Bus 1 Free 8 Bits 4 7 Reserved Bits 0 3 Clock Bus 3 Events These bits indicate pending Clock Bus 3 requests arrived from the shelf manager 0 Clock Bus 3 Query 1 Clock Bus 3 Release 2 Clock Bus 3 Force 3 Clock Bus 3 Free Table 8 29 Get Status Command Description con...

Page 293: ... Table 8 28 0x04 Reset the IPMC and enter Upgrade mode Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 30 Reset IPMC Command Description continued Type Byte Data Field Table 8 31 Get Serial Interface Properties Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterp...

Page 294: ... Reserved Bits 3 0 Baud Rate ID The baud rate ID defines the interface baud rate as follows 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps unsupported 4 115200 bps unsupported Table 8 31 Get Serial Interface Properties Command Description continued Type Byte Data Field Table 8 32 Set Serial Interface Properties Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise I...

Page 295: ...pported 4 115200 bps unsupported Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 32 Set Serial Interface Properties Command Description continued Type Byte Data Field Table 8 33 Get Debug Level Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A ...

Page 296: ...f IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert Logging Enable If set to 1 the IPMC outputs important alert messages onto the serial debug interface Bit 1 Low level Error Logging Enable If set to 1 the IPMC outputs low level error diagnostic messages onto the serial debug interface Bit 0 Error Logging Enable If set to 1 the IPMC outputs error diagnostic me...

Page 297: ...ving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert Logging Enable If set to 1 the IPMC outputs important alert messages onto the serial debug interface Bit 1 Low level Error Logging Enable If set to 1 the IPMC outputs low level error diagnostic messages onto the serial debug interface Bit 0 Error Logging Enable If set to 1 the IPMC outputs error diagnostic messages onto the serial debug ...

Page 298: ...ta 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Hardware Address Table 8 36 Set Hardware Address Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterpr...

Page 299: ... first byte 2 0A byte 3 40 byte 4 00 Table 8 36 Set Hardware Address Command Description continued Type Byte Data Field Table 8 37 Get Handle Switch Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394...

Page 300: ...94 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 39 Get Payload Communication Time Out...

Page 301: ... Communication Time Out Command Description continued Type Byte Data Field Table 8 40 Set Payload Communication Time Out Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Payload Time out Payload communication time out measured in hundreds of milliseconds Thus the payload commu...

Page 302: ...ta 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 42 Disable Payload Control Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A ...

Page 303: ...elf manager Otherwise the 0xCC completion code is sent The IPMC does not reset the payload upon receiving the Graceful Reset command or time out If the IPMC participation is necessary the payload must request the IPMC to perform a payload reset The Graceful Reset command is also used to notify the IPMC about the completion of the payload shutdown sequence Table 8 43 Hang IPMC Command Description T...

Page 304: ...cur if the payload software does not respond the IPMC provides a special time out for the payload shutdown sequence If the payload does not send the Graceful Reset command within a definite period of time the IPMC assumes that the payload shutdown sequence is finished and resets the payload Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB B...

Page 305: ...Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 5 Time Out measured in hundreds of milliseconds LSB first Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 47 Get Module State Command Description Type Byte Data Field Request Data 1 3 PPS IANA Pr...

Page 306: ... is disabled 1 Management power is enabled Bit 3 0 Management power is bad 1 Management power is good Bit 4 0 Payload power is disabled 1 Payload power is enabled Bit 5 0 Payload power is bad 1 Payload power is good Bit 6 0 IPMB L buffer is not attached 1 IPMB L buffer is attached Bit 7 0 IPMB L buffer is not ready 1 IPMB L buffer is ready Table 8 47 Get Module State Command Description continued ...

Page 307: ...equest Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Module Site ID Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Table 8 49 Disable Module Site Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private E...

Page 308: ... the carrier SDR repository Table 8 50 Reset Carrier SDR Repository Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 ...

Page 309: ...ands and provides hardware interfaces for other system management features such as Hot Swap control LED control power control as well as temperature and voltage monitoring The IPMC also supports a Keyboard Controller Style KCS based host interface for direct payload to IPMI communication The ATCA 7490 provides a rich feature set Carrier SDR Repository FRU inventory Sensor Management BIOS FPGA Boot...

Page 310: ...mmands directed to the MMC will be bridged by the IPMC The Intel CPU communicates with the IPMC using the KCS interface of the IPMC The FRU inventory System Event Log SEL events and the SDR information are stored in external I2C EEPROMs This enables post mortem analysis when the system processor becomes disabled Registers within the Glue Logic FPGA can be accessed by the IPMC via I2C bus This enha...

Page 311: ...MC block diagram of ATCA 7490 IPMB 0 I2C IPMB A IPMB B IPMB L I2C B u f f e r B u f f e r LPC Microsemi A2F200M3F_CS2 88 IPMC PCH ME 0x96 0x98 Intel CPU Intel NIC SOL ATMEGA 128 MMC at RTM NCSI Lattice GLUE FPGA 0xFD 0xFE FRU EEPROM 0xA2 SEL EEPROM 0xA0 PIM 0x50 PCA9555 0x48 WDT WDT Cortex M3 ADT ADT LM75 outlet LM75 inlet LM75 TEMP Front Front RTM I2C ...

Page 312: ...is responsible for providing a means for measuring time and detecting timeout conditions The device drivers are responsible for implementing high level interfaces to the hardware Network Stack The Network Stack is provided to implement RMCP protocols for IPMI over LAN and Serial over LAN Application Layer The Application layer is implemented as a multi threaded application The main thread reads in...

Page 313: ...tSwap Management IPMC x Sensor Management x FRU Inventory x Carrier SDR Repository IPMC x KCS IPMB 0 IPMB L Interface Communication x Standalone Mode Application Layer x IRQ Handlers x Low Level Initialization x I O Device Drivers Active IPMI firmware x FRU HotSwap Management IPMC x Sensor Management x FRU Inventory x Carrier SDR Repository IPMC x KCS IPMB 0 IPMB L Interface Communication x Standa...

Page 314: ...is made in flash Once the new IPMI firmware is programmed the IPMI controller will reset itself to boot from the new image Also the boot loader validates new IPMI firmware images Provided IPMI controller can power up successfully the current image is made active and the previously active image is made backup In case power up fails the boot loader will automatically recover from crisis and boots fr...

Page 315: ...s one is designated Active the other one is Backup During power up the IPMC protects the Active SPI flash by de selecting it once the FPGA boots successfully Thus HPM 1 specific logic updates can be performed only to the Backup SPI flash By explicitly prohibiting FPGA logic updates to the Active SPI flash crisis recovery is guaranteed always Both FPGA flashes cannot be overwritten incorrectly even...

Page 316: ...ted via failsafe architecture For details see Fail Safe Logic on page 349 The HPM 1 command Activate Firmware does not reboot the payload firmware unconditionally Instead the blade can be rebooted gracefully to activate the firmware Crisis recovery is supported fully two broken SPI flashes can be reprogrammed via IPMI with the help of the ShMM 9 2 2 Retrieving Version Information Retrieving the ac...

Page 317: ...on 0 00 00000001 Bank 1 Rollback Version 0 00 00000001 Bank marked for next use 0 05 Device RTM IPMI F W Bank 0 Active Version 2 00 00000004 Bank 1 RollbackVersion 2 00 00000004 06 Device RTM IPMI B L Bank 0 ActiveVersion 2 00 00000004 07 Device RTM IPMI F I 08 Device RTM HA EE Bank 0 Active Version 0 01 00000000 09 Device atca 7490 cpu Bank 1 Active Version 0 3 00000000 Bank 0 Rollback Version 0 ...

Page 318: ...8 13 pps2 perform the following steps Procedure 1 Get the Pigeon Point System ipmitool from the package ipmitool 1 8 13 pps 2 tgz 2 Extract the ipmitool 1 8 13 pps 2 tgz file prompt tar xzvf ipmitool 1 8 13 pps 2 tgz 3 Go to the directory where ipmitool is extracted prompt cd path Ipmitool 1 8 13 pps 2 4 Build the ipmitool prompt configure make make install If ipmitool 1 8 13 pps2 is already insta...

Page 319: ...powered on M4 The BASE Ethernet controller is powered with management power 9 2 3 3 1 KCS The standard way to upgrade the firmware of the payload is through the KCS interface The IPMC implements the KCS communication protocol to communicate with the Intel host CPU For detailed description of the KCS read write data flow please refer to IPMI specification section 9 Example prompt ipmitool hpm upgra...

Page 320: ...rades the IPMC is complaint to the HPM 2 specification and supports large IPMI messages over LAN interfaces via base interface and from payload host Thus firmware upgrades can be executed much faster This is especially useful with BIOS firmware upgrades when 16 Mbytes of data need to be transferred via IPMI The following example is provided to enable users to upgrade their firmware very quickly fr...

Page 321: ...TCA7490 ifconfig base1 1 172 16 0 70 3 Upgrade the firmware root ATCA7490 ipmitool C 1 I lanplus U rmcp P rmcp H 172 16 0 221 k gkey hpm upgrade root bios hpm activate PICMG HPM 1 Upgrade Agent 1 0 9 Validating firmware image integrity OK Performing preparation stage Services may be affected during upgrade Do you wish to continue y n y OK Performing upgrade stage ID Name Versions Active Backup Fil...

Page 322: ...ensor type name supported thresholds assertion and de assertion information and a brief description of the sensor purpose Table 9 2 ATCA 7490 Specific Sensors Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Event Data Byte 2 Event Data Byte 3 Event Threshold Description Assertion Deassertion Rearm 0 Hot Swap Carrier Hot Swap 0xF0 Sensor specific discrete 0x6F 0x0 0x1 0x2...

Page 323: ...l Physical IPMB 0 0xF1 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 7 4 Channel Number 3 0 Reserved reading 0x0 IPMB A disabled IPMB B disabled 0x1 IPMB A enabled IPMB B disabled 0x2 IPMB A disabled IPMB B enabled 0x3 IPMB A enabled IPMB B enabled Asrt Auto Table 9 2 ATCA 7490 Specific Sensors continued Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Event Data Byte 2 E...

Page 324: ...ul Asrt Auto 4 Mid air temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 5 3 3V MGMT Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 6 12V Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 7 5V Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 8 RTM 3 3 MGMT Voltage 0x02 Threshold 0x01 reading ...

Page 325: ...c discrete 0x6F 0x0 0x1 0x2 0x3 0x8 See IPMI Spec 0xFF 0x0 Timer expired 0x1 Hard Reset 0x2 Power Down 0x3 Power Cycle 0x8 Timer Interrupt Asrt Auto 13 FW Progress System Firmware Progress 0x0F Sensor specific discrete 0x6F 0x0 0x1 0x2 See IPMI Spec See IPMI Spec 0x0 System Firmware Error 0x1 System Firmware Hang 0x2 System Firmware Progress Asrt Auto Table 9 2 ATCA 7490 Specific Sensors continued...

Page 326: ...t completed 0x6 bootcompleted Asrt Auto 15 Boot Error Boot Error 0x1E Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0xFF 0xFF 0x0 No Bootable media 0x1 Non bootable diskette 0x2 PXE Server not found 0x3 Invalid boot sector 0x4 Timout waiting for user selection Asrt Auto Table 9 2 ATCA 7490 Specific Sensors continued Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Eve...

Page 327: ...0x7 0xFF 0xFF 0x0 Correctable ECC 0x1 Uncorrectable ECC 0x4 Memory Device Disabled 0x5 Correctable ECC 0x6 Presence detected 0x7 Configuration error Asrt Auto 18 Critical IRQ Critical Interrupt 0x13 Sensor specific discrete 0x6F 0x4 0x5 0xFF 0xFF 0x4 PCI PERR 0x5 PCI SERR Asrt Auto 19 Battery Battery 0x29 Sensor specific discrete 0x6F 0x1 0xFF 0xFF 0x1 Battery failed Asrt Auto Table 9 2 ATCA 7490 ...

Page 328: ...1 Power Supply Failure detected Asrt Auto 23 48v A Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 24 48v B Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 25 48v Amps Current 0x03 Threshold 0x01 reading threshold No Thresholds Auto 26 HoldUp Cap Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 27 ...

Page 329: ...er Supply Failure detected Asrt Deass Auto 30 48V B Supply Power Supply 0x08 Sensor specific discrete 0x6F 0x0 0x1 See IPMI Spec 0xFF 0x0 Presence detected 0x1 Power Supply Failure detected Asrt Deass Auto 31 BIOS POST code OEM 0xD1 Sensor specific discrete 0x6F 0x0 0x0 No events for this sensor Reading accordingtoEFIBIOS port80 status codes Asrt Auto Table 9 2 ATCA 7490 Specific Sensors continued...

Page 330: ...0 Payload Reset detected Cause delivered in Event Byte 2 3 Asrt Auto 33 ACPI State System ACPI Power State 0x22 Sensor specific discrete 0x6F 0x0 0x3 0x5 0xFF 0xFF 0x0 S0 0x3 S3 0x5 S5 Asrt Auto 34 CPU Status Processor 0x07 Sensor specific discrete 0x6F 0x0 0x1 0xFF 0xFF 0x0 IERR 0x1 Thermal Trip Asrt Auto Table 9 2 ATCA 7490 Specific Sensors continued Sensor Number Sensor Name Sensor Type Event R...

Page 331: ...lure state 0x0 ME_OFF 0x2 ME_ON 0x3 ME_PWR 0x4 ME_WAIT 0x5 ME_WAIT_OF Other These values will never occur 6 3 Reserved 7 ME Failure Asrt Auto Table 9 2 ATCA 7490 Specific Sensors continued Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Event Data Byte 2 Event Data Byte 3 Event Threshold Description Assertion Deassertion Rearm ...

Page 332: ..._VPP_EN ABLE 0xB VDDQ_ENABLE 0xC VP12_ON 0xD VTT_ENABLE 0xE WAIT_100MS Other These values will never occur 6 5 Reserved 0x7 Pyld Power Fail Asrt Auto 37 PYLD Pwr Fail C1 OEM 0xE2 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x7 0xFF 0xFF 0x0 Pyld Wake UP Fail 0x1 VCCIO PG Fail 0x2 Reserved 0x7 Thermtrip Asrt Auto Table 9 2 ATCA 7490 Specific Sensors continued Sensor Number Sensor Name Sensor Type Eve...

Page 333: ...42 DDR1 J11 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 43 DDR2 J12 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 44 DDR3 J13 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 45 DDR4 J14 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 46 DDR5 J15 temp Temp 0x01 Threshold 0x01 reading th...

Page 334: ... unr uc unc Asrt Deass Auto 54 DDR13 J25 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 55 DDR14 J26 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 56 DDR15 J27 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 57 DDR16 J28 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 58 PCH temp Temp 0x0...

Page 335: ...Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto Table 9 2 ATCA 7490 Specific Sensors continued Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Event Data Byte 2 Event Data Byte 3 Event Threshold Description Assertion Deassertion Rearm ...

Page 336: ...e firmware progress sensor implemented with sensor type 0x0F System Firmware Progress is used to pass payload boot progress information to the IPMC Figure 9 3 Temperature Sensors Location DIMM5 Temp J15 DIMM6 Temp J16 DIMM7 Temp J17 DIMM8 Temp J18 DIMM4 Temp J14 DIMM3 Temp J13 DIMM2 Temp J12 DIMM1 Temp J11 DIMM9 Temp J21 DIMM10 Temp J22 DIMM11 Temp J23 DIMM12 Temp J24 DIMM16 Temp J28 DIMM15 Temp J...

Page 337: ...ow failed RTC The Critical IRQ sensor implemented with sensor type 0x13 Critical Interrupt is used to give PCI errors and NMIs The boot error sensor implemented with sensor type 0x1E Boot Error is used to pass boot failure information to the IPMC In all cases above the IPMC sends an event to the ShMM 9 3 2 Boot Bank Supervision Sensor The boot bank supervision sensor is intended to always give the...

Page 338: ...tively transition the IPMC from M4 to M6 to M1 with a cause code of 0x09 Unexpected Deactivation This automatic shutdown is meant to keep the IPMC s state in line with the payload state 9 3 5 Power Interface Sensors An Ericsson Power input module PIM4328 is used for the 48v to 12v conversion monitoring The PIM includes sensors which monitor the shelf s 48v input feeds current hold up capacitor vol...

Page 339: ... State 0 Primary side Alarm is not set 1 Primary side Alarm is set Bit 1 Voltage Feed B Enabled 0 Enable B is Disabled 1 Enable B is Enabled Bit 0 Voltage Feed A Enabled 0 Enable A is Disabled 1 Enable A is Enabled Table 9 4 Status Sensor s Sensor Reading continued Bit Type Status Description Table 9 5 Voltage and Temperature Sensor Devices I2C address I2C bus Domain Purpose Device 0x50 IPMC priva...

Page 340: ...e payload domain When a Payload Power failure occurs the red power failure LED is switched ON signal PWR_FAIL_ is driven low The power failing state is maintained until Payload power is turned off Manual Powering Setting the switch SW 100 1 from ON to OFF IPMC Controlled Powering The IPMC shutting down the payload power signal IPMC_VP48_EN_ is deserted For more information see Table 5 49 For all p...

Page 341: ...erted or a cold IPMI Command reset is performed POST verifies the functionality of SRAM IPMB 0 EEPROM data storage FRU Information and all devices primarily sensors attached to the IPMC s private master only I2C bus A detailed description of POST tests are as follows FRU InformationU Verifies that the FRU Information is readable from the external EEPROM where it is stored Once read each section s ...

Page 342: ...wo intelligent FRUs IPMC and MMC Every FRU provides its own FRU information serial part MAC addresses Depending on the presence of a module its FRU information is visible or not TheFRUoftheRTMisnothot swappable Thisisespeciallyimportanttoensurethatthesystem management application HPI B does not has to deal with dynamic FRU population The MAC addresses of a FRU are stored within the multi record ar...

Page 343: ... ID Write as CDh 6 1 Second Byte of Manufacturer ID Write as 65h 7 1 MSB of Manufacturer ID Write as 00h 8 1 Artesyn Record ID 01h for Artesyn MAC Address Record 9 1 Record Format Version 01h for this specification 10 1 Number of MAC Address Descriptors N 11 N 9 Artesyn MAC Address Descriptors Refer to XTable 7 Artesyn MAC Address Descriptor Table 9 8 Artesyn MAC Address Descriptor Offset Length D...

Page 344: ...9 9 Interface Type Assignments Interface Type Description 01h ATCA Base Interface 02h ATCA Fabric Interface 03h Front Rear Panel 04h Mezzanine Module 05h Serial over LAN SOL 06h Fibre Channel WWPN 07h AMC MicroTCA Common Options Region 08h AMC MicroTCA Fat Pipe Region 09h AMC MicroTCA Extended Fat Pipe Region 10h ATCA Update Channel 11h Multi type Base Fabric and Update channel or two types of it ...

Page 345: ...he Product Version Item Value Description Dynamic power reconfiguration support No While the blade is powered itsupportsonly one power level Dynamic power configuration No The power level is fixed and does not change Number of power draw levels 1 The amount of possible power levels Early Power Draw Levels Watt Complete early power level including IPMC Steady state Power Draw Levels Watt CFG0000 75...

Page 346: ...tem manager may decide from which boot device the blade should boot from The boot configuration parameters are stored as sets of parameter name and value pairs They can be easily enhanced and there are no dependencies between different versions of IPMC firmware and payload firmware The IPMC provides a set of boot configuration parameters and the payload firmware just initializes those he knows abo...

Page 347: ...ctions before the payload is gracefully rebooted shut down Graceful Reboot and Graceful Shutdown is also communicated to the Intel CPU via internal communication channel 9 11 Serial Line Selection TheATCA 7490providestwoserialinterfacesfrompayload Bydefault thefirstisroutedtothe front connector and the second to the RTM In addition there is an IPMC debug interface which can be routed either to the...

Page 348: ... active and standby is done by the IPMC TheBIOSBootBankSelectionisimplementedsuchthatswappingtheSPIflashesisnotineffect immediately To ensure that the active BIOS bank cannot be overwritten at all BIOS upgrades always can just access the backup boot bank the boot bank selection is masked with a payload reset Therefore swapping the boot bank is possible with the following steps only Swap the BIOS b...

Page 349: ...ion and parameter 224 For details see Set Feature Configuration on page 286 BIOS setup menu Typically failsafe is used to protect a BIOS firmware upgrade to recover even when the boot image programmed does not work is damaged or has an unpredictable error Failsafe is implemented within the IPMI management controller In case the firmware does not bootandtheBMCwatchdogexpires theIPMImanagementcontro...

Page 350: ...cover from scenarios Missing or defect boot block Firmware image has a bad checksum Figure 9 4 FailSafe Swap Boot Bank and send a System Firmware Hang event to the ShMM Start Send a BMC Watchdog event to the ShMM Reboot the blade Yes Yes Yes Watchdog expired Failsafe enabled Failsafe count 3 ...

Page 351: ... Logic FPGA Flash Selection The ATCA 7490 provides redundant FPGA flashes for both manual and automatic crisis recoveries The general concept is that there is always an active and a standby SPI flash device The role of these two devices can be reversed by the IPMC for this to work the IPMC has to drive the chip select signals to the SPI flashes The final decision about which of the two devices is ...

Page 352: ... page 337 9 13 2 Fail Protect Logic Fail Protect is a mechanism implementing automatic FPGA bank crisis recovery It observes the FPGA boot phase to swap the FPGA banks and to reload the FPGA in case of the FPGA firmware hangs accidentally Fail Protect can be enabled or disabled at any time using an IPMI OEM command called Set Get Feature Configuration and parameter 224 For details see Set Feature ...

Page 353: ...ired Failed once start Deassert signal FPGA_PROGRAM Evaluate signal FPGA Done Yes Yes Yes Both FPGA banks corrupted Crisis Recovery FPGA Load Done Swap Boot Bank to protect working image Remote Crisis Recovery Mode M1 Success Select Boot Bank from NVRAM Set Timer send a System Firmware Hang event to the ShMM Set failprotect to FAILED_ONCE Set failprotect to FAILED_TWICE ...

Page 354: ...vent Reading Type Code 0x6F Sensor Specific Event Data Byte 1 0xA1 System Firmware Hang Event Data Byte 2 0x00 CPU instance Event Data Byte 3 0xXX Failed Boot Bank ID 0 Bank A 1 Bank B Payload software is able to detect when Fail Protect was activated during last boot For details see Table 8 26 By default Fail Protect is activated 9 13 3 Remote Crisis Recover Mode This mode is entered when both FP...

Page 355: ...ry in the buffer All events are automatically logged locally to the local SEL before being passed to the Shelf s SEL which includes all events that occur from the local MMC To support the local SEL a software emulated RTC Real Time Clock is enabled which upon startup requests the local time from the shelf manager by sending an IPMI standard command Get SEL Time Once the initial time is received th...

Page 356: ...IPMI Feature Set ATCA 7490 Installation and Use 6806800U11F 356 ...

Page 357: ...acing the Battery Some blade variants contain a on board battery of type CR2032 Its location is shown in the following figure A battery less variant based on SUPERCAP is available on demand Figure A 1 Location of On board Battery P30 P31 P32 P22 P20 P23 P40 P10 P33 Battery Location Goldcap ...

Page 358: ...ss If the battery does not provide enough power anymore the RTC is initialized and the data in the NVRAM is lost Therefore replace the battery before seven years of actual battery use have elapsed Data Loss Replacing the battery always results in data loss of the devices which use the battery as power backup Therefore back up affected data before replacing the battery Data Loss If installing a dif...

Page 359: ...ce the battery 1 Remove battery 2 Install the new battery according to the positive and negative signs PCB and Battery Holder Damage Removing the battery with a screw driver may damage the PCB or the battery holder To prevent this damage do not use a screw driver to remove the battery from its holder ...

Page 360: ...Replacing the Battery ATCA 7490 Installation and Use 6806800U11F 360 ...

Page 361: ... persistent after the board is powered down Table B 1 ATCA 7490 Nonvolatile Memory Type Size Use Procedure SPI Flash Processor 16MB x 2 Default and Backup BIOS Images See note below SPI Flash IPMC 4MB IPMC Firmware See Procedure below FPGA SPI Flash 512KB x 2 FPGA Configuration See note below IPMC I2C EEPROM 64KB Board FRU Data See note below IPMC I2C EEPROM 64KB SEL Data See note below SPI Flash ...

Page 362: ...ervices rom The utility that will be used to initialize the nonvolatile memory devices is called fcu Details of the command can be found in section FCU Firmware Upgrade Command Line Utility in the same manual referenced above The procedures outlined below to update the nonvolatile memory images can also be referenced in the same manual under section Upgrading a Firmware Image B 1 1 SPI Flash Proce...

Page 363: ... with your local sales team to determine the correct image to use The example below is based on a supplemental BIOS upgrade released after the BBS release ATCA 737 root cd opt bladeservices rom ATCA 7490 opt bladeservices rom BIOS fcu u f atca 7490_standard_bios_01_03_0007 fri datca 7490 cpu REPORT BEGIN Operation Upgrade erasing 100 writing 100 Result Success REPORT END To switch to the new image...

Page 364: ... to program the BMC micro controller The flash is divided to support an active and a standby image As with the other processor flash device it requires a special algorithm to access the flash Accidentally writing classified data to these devices is not possible DeclassificationofthisflashdeviceisthesameaswiththeSPIFlashdescribedabove Theimage to update the device can be found in the same location ...

Page 365: ...h associated with the IPMC controller is used to store user defined BIOS variables that are also accessible from a higher level operating system utility called hpmcmd which is part of Artesyn s Basic Blade Services Linux environment mentioned above Configuration information normally stored while operating in the BIOS can be done using this command while the board is running Linux It can store conf...

Page 366: ...utilizes the fpga_upg utility included with the ATCA 7490 base software As with the other devices listed previously the Install_7490_Software sh automatically will update the microcode sections of these devices with the default images To verify the device contents the following commands can be used ATCA 7490 opt bladeservices rom fcu u match product table f atca7490_em_fpga _10_00_0000 hpm REPORT ...

Page 367: ...lt and can only be changed by special algorithms Accidentally writing classified data to these devices is not possible A checksum is loaded into the FRU data section whenever FRU data is loaded into the board To verify that the FRU data has not changed run fcu q d atca 7490 cpu and verify that there are no checksum error messages displayed The easiest method to recover the FRU data on the board is...

Page 368: ...hese are MO 297 Slim SATA solid state storage devices that can be added to the board and are optional They behave like normal solid state hard drives They can be removed and destroyed or cleared using any standard Linux based software application like dd The basic procedure to clear this type of device is to dd if dev zero of dev sda bs 1M ...

Page 369: ...roduct documentation 1 Go to www artesyn com computing support product technical documentation php 2 Under FILTER OPTIONS click the Document types drop down list box to select the type of document you are looking for 3 In the Search text box type the product name and click GO Table C 1 Artesyn Embedded Technologies Embedded Computing Publications Document Title Publication Number ATCA 7490 Quick S...

Page 370: ...ollowing table for related specifications As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table C 2 Manufacturer s Documents Company Document Title Intel Xeon Processor E5 v4 Product Family External Design Spec Vol 1 3 Intel Ethernet Switch FM10000 Datasheet Intel C610 Ser...

Page 371: ......

Page 372: ...esyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2018 Artesyn Embedded Technologies Inc ...

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