Artesyn Embedded Technology ATCA-7490, Installation And Use Manual

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Functional Description
ATCA-7490 Installation and Use (6806800U11F)
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For DDR4-2400 (PC4-2400) DIMMS
– 1 DIMM Per Channel (DPC) – Speed up to PC4-2400
– 2 DPC – Speed up to PC4-2133 (Due to Memory Channel Loading)
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For DDR4-2133 (PC4-2133) DIMMS
– 1 DPC – Speed up to PC4-2133 (Due to Memory speed limit)
– 2 DPC – Speed up to PC4-2133 (Due to Memory speed limit and Channel Loading)
The following are the supported memory features:

RAS features supported with Error Correction Code (ECC) (Mirroring, x8/x4 SDDC, Sparing,
Scrubbing)
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Memory Error signaling for uncorrectable errors
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Memory Error signaling for correctable memory errors
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Asynchronous DRAM Refresh (ADR) feature to support persistent memory structures in
DDR4 (asynchronous DRAM refresh)
4.4 Platform Controller Hub Intel C612 Wellsburg
The Next Generation Communications Platform Controller Hub (codename Wellsburg) Intel
C612 PCH provides access between processors and the I/O subsystem. The PCH connects to
CPU#0 through Intel DMI2.0, PCH I/O-controller connected to DMI2 interface of CPU#0.
ATCA-7490 supports Intel Hybrid Clocking Mode through the Intel C612 PCH controller. By
default, the Spread Spectrum Clocking (SSC) feature is enabled for the 100MHz CPU and the
PCIe clocks, which are provided by the Intel C612 and buffered through DB1900 buffer. If SSC
is enabled in BIOS settings, all PCIe devices that are connected on-board or via RTM module will
receive SSC clock. SSC can be disabled using BIOS settings.
The SSC tolerance is +/-0.25% from nominal frequency (100 MHz).
When mixing DIMMs of different speed selections, BIOS will select the lowest speed for
all memory channels/DIMM slots on a per CPU level basis.