Artesyn Embedded Technology ATCA-7490, Installation And Use Manual

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Maps and Registers
ATCA-7490 Installation and Use (6806800U11F)
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0x20 - w NMI Generation Register (See, Table 5-69 )
0x20 r/w1c - NMI Interrupt Status Register (See, Table 5-70 )
0x21 r/w1c w Internal Interrupt Status Register (See, Table 5-71 )
0x22 r - Telecom Interrupt Status Register (See, Table 5-72 )
0x23 r/w - Telecom Interrupt Control Register (See, Table
5-73 )
0x24 r - External Interrupt Status Register (See, Table 5-74 )
0x25-0x27 r/w - Interrupt Mask and Map Registers (See, Chapter 5,
Interrupt Mask and Map Registers )
0x30- 0x37 r/w r/w CPU0 Hot Plug I2C IO Expander Registers (See,
Chapter 5, CPU0 Hot Plug I2C IO Expander Registers )
0x38-0x3F r/w r/w CPU1 Hot Plug I2C IO Expander Registers (See,
Chapter 5, CPU0 Hot Plug I2C IO Expander Registers )
0x40 r r/w Flash Status Register (See, Table 5-82 )
0x41 r/w r PCH Output Enable Register (See, Table 5-83 )
0x42 r/w - RTM SPI Address/Command Register (See, Table
5-84 )
0x43 r/w - RTM SPI Write Register ( Table 5-85 )
RTM SPI Read Register (See, Table 5-86 )
0x48 r/w r Update Channel Equalization Control Register (See,
Table 5-87 )
0x4A r/w r RTM USB Control Register (See, Table 5-88 )
0x4B - r RTM Status Register (See, Table 5-89 )
0x4C - r/w1c RTM Interrupt Status Register (See, Table 5-90 )
0x50 r/w r LED Control Register (See, Table 5-91 )
0x52 r r Spare Signal Status Register (See, Table 5-92 )
0x54 r r CPU Presence Detection Register (See, Table 5-93 )
0x57 r r CPU Error Status Register (See, Table 5-94 )
Table 5-38 FPGA Register Map Overview (continued)
LPC Address Offset LPC I/O IPMC I2C Description