Artesyn Embedded Technology ATCA-7490, Installation And Use Manual

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Maps and Registers
ATCA-7490 Installation and Use (6806800U11F )
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The FPGA emulates the PCA9555 device. Each CPU has two devices attached to the
corresponding I2C bus (SMBus). The I2C slave addresses are 0x20 for the first device and 0x21
for the second device.
5.1.19.4 PCA9555 Internal Register access
For debug purpose the internal virtual PCA9555 registers can be read by the IPMC and the
Service Processor.
5.1.20 Flash Status and Selection Registers
The flash status register indicates the actual status of the mechanical switches SW1.3 (Signal
BOOT_TSOP), SW3.1 (Signal BOOT_SEL_EN_) and SW3.2 (Signal BOOT_DEFAULT).
Table 5-80 Address Control for PCA9555 Internal Register
Address Offset:
CPU0 Device1 (Slave address 0x20): 0x34
CPU0 Device2 (Slave address 0x21): 0x36
CPU1 Device1 (Slave address 0x20): 0x3C
CPU1 Device1 (Slave address 0x21): 0x3E
Bit Description Default Access
2:0 Internal PCA9555 register address 0 r/w
7:3 Reserved 0 r
Table 5-81 Content of PCA9555 Internal Register
Address Offset:
CPU0 Device1 (Slave address 0x20): 0x35
CPU0 Device2 (Slave address 0x21): 0x37
CPU1 Device1 (Slave address 0x20): 0x3D
CPU1 Device1 (Slave address 0x21): 0x3F
Bit Description Default Access
7:0 Content of PCA9555 register. 0 r