Artesyn Embedded Technology ATCA-7370, Installation And Use Manual

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Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54G )
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6.2.5.4 Interrupt Identification Register (IIIR)
In order to minimize software overhead during data character transfers, UART prioritizes
interrupts into four levels and records these in the IIIR. The IIIR stores information indicating
that a prioritized interrupt is pending, as well as the source of that interrupt. The four levels are
listed in the succeeding table.
Table 6-31 UART Interrupt Priorities2
Priority Level Interrupt Source
1 (highest) Receiver Line Status. One or more error bits were set.
2 Received Data is available. In FIFO mode, trigger level was reached; in non-FIFO
mode, RBR has data.
2 Receiver Time out occurred. It happens in FIFO mode only, when there is data in the
receive FIFO but no activity for a time period.
3 Transmitter requests data. In FIFO mode, the transmit FIFO is half or more than half
empty; in non-FIFO mode, THR is read already
4 Modem Status: one or more of the modem input signals has changed state
Table 6-32 Interrupt Identification Register (IIIR)
LPC IO Address: Base + 2
Bit Description Default Access
0 Interrupt status bit:
1: no interrupt pending
0: interrupt pending 1 LPC: r
2:1 Interrupt priority level and source:
11: Receiver line status
10: Receiver data available
01: Transmitter holding register empty
00: Modem status 0 LPC: r
3 Time Out Detected:
0: No time out interrupt is pending
1: Character time-out indication (FIFO mode
only) 0 LPC: r