Artesyn Embedded Technology ATCA-7370, Installation And Use Manual

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Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54G )
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Following table defines how to determine the cause of an interrupt in the processor.
6.2 Registers
For register description, the convention shown in Table 6-7 "Register Access Type" and Table 6-7
"Register Access Type" are used.
Table 6-5 Causes of Interrupt
Condition Cause
Recommended Platform
Software Response
MC_SMI_DIMM_ERROR_STATU
S.
DIMM_ERROR_OVERFLOW_ST
ATUS !=0 The register has one bit for each
DIMM error counter that
exceeds threshold.
This can happen at the same
time as any of the other SMI
events (Sparring complete,
redundancy lost in Mirror
Mode) Examine the associated
MC_COR_ECC_CNT_X register.
Determine the time since the
counter has been cleared. If a
spare channel exists, and the
threshold has been exceeded
faster than would expected
given the background rate of
correctable errors, sparing
should be initiated. The counter
should be cleared to reset the
overflow bit.
MC_RAS_STATUS.REDUNDANC
Y_LOSS = 1 One channel of a mirrored pair
had an uncorrectable error has
been lost. Raise an indication that a reboot
should be scheduled, possibly
replace the failed DIMM
specified in the
MC_SMI_DIMM_ERROR_STATU
S register.
MC_SSRSTATUS. CMPLT = 1 A sparring copy operation set up
by software has completed. Advance to the next step in the
sparing flow.
Table 6-6 Register Default
Default Description
- Not applicable or undefined
0 or 1 Default value after RST_N is valid or after PCH_PLTRST deassertion.
Undef. Undefined value