Artesyn Embedded Technology ATCA-7370, Installation And Use Manual

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Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54G )
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6.2.3 Super IO Configuration Register
After a LPC Reset (ICH_PLTRST_ is asserted) or "Power On Reset" the Super IO is in the Run Mode
with the UARTs disabled. They may be configured using the LPC IO Address Range SIW (INDEX
and DATA) by placing the Super IO into Configuration Mode. The BIOS uses these configuration
addresses to initialize the logical devices at POST. The INDEX and DATA addresses are only valid
when the Super IO is in Configuration State. The INDEX and DATA addresses are effective only
when the Super IO is in the Configuration State. When the Super IO is not in the Configuration
State, reads return 0xFF and write data is ignored.
6.2.3.1 Entering the Configuration State
The device enters the Configuration State by the following contiguous sequence:
1. Write 80H to Configuration Index Port.
2. Write 86H to Configuration Index Port.
6.2.3.2 Exiting the Configuration State
The device exits the configuration state by the following contiguous sequence:
1. Write 68 to Configuration Index Port.
2. Write 08 to Configuration Index Port
Table 6-11 Super I/O Configuration Index Register
LPC I/O Address: 0x4E
Bit Description Default Access
7:0 INDEX. Configuration Index. 0xff LPC: r/w
Table 6-12 Super I/O Configuration Data Register
LPC I/O Address: 0x4F
Bit Description Default Access
7:0 DATA Configuration Data. 0xff LPC: r/w