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Artesyn Embedded Technology ATCA-7370, Installation And Use Manual

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Maps and Registers

ATCA-7370/ATCA-7370-S Installation and Use (6806800P54G)

119

The chipset has NMI Status and Control Register and the NMI Enable Register. Both can be used 
to configure the relevant settings and get the status report. Software can also set NMI2SMI_EN 
bit in TC01 Control Register to force all NMIs to instead cause SMI. The functionality of this bit 
is dependent upon the settings of the NMI_EN bit and the GBL_SMI_EN bit, as detailed in the 
succeeding table. 

IPMC can initiate a NMI request to processor to cause a warm-reset when the Payload-
Watchdog in IPMC is timeout or when IPMC receives a command from shelf-manager.

In Intel Xeon E5-2648L Processor, either SMI or NMI interrupts can be enabled in 
MC_SMI_CNTRL register. The type of interrupt trigger is based on the following conditions or 
scenarios:

A DIMM error counter exceeds the threshold

Redundancy is lost on a mirrored configuration or

A sparing operation completes.

Warm reset request.

This register is set by hardware once operation is complete. Bit is cleared by hardware when a 
new operation is enabled. An SMI is generated when this bit is set due to a sparing copy 
completion event.

NMI_EN

GBL_SMI_EN

Description

0b

0b

No SMI# at all because GBL_SMI_EN = 0

0b

1b

SMI# will be caused due to NMI events

1b

0b

No SMI# at all because GBL_SMI_EN = 0

1b

1b

 No SMI# due to NMI because NMI_EN = 1

Summary of Contents for ATCA-7370

Page 1: ...ATCA 7370 ATCA 7370 S Installation and Use P N 6806800P54G September 2014 ...

Page 2: ...hanges from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without ...

Page 3: ... Preparation and Installation 45 2 1 Unpacking and Inspecting the Blade 45 2 2 Environmental and Power Requirements 45 2 2 1 Environmental Requirements 46 2 2 2 Power Requirements 49 2 3 Blade layout 51 2 4 Installing the Blade Accessories 52 2 4 1 DIMM Memory Modules 52 2 4 2 Cave Creek Module 54 2 5 Installing and Removing the Blade 57 2 5 1 Installing the Blade 57 2 5 2 Removing the Blade 59 3 ...

Page 4: ...on 79 4 1 5 I O Device Configuration 79 4 1 5 1 Serial Ports 79 4 1 5 2 Integrated SATA Controller 79 4 1 6 Boot Options 80 4 1 6 1 Boot Support for the SAS Controller 80 4 1 6 2 Network Boot 81 4 1 7 I O Redirection 82 4 1 8 Console Redirection 82 4 1 9 Serial Over LAN SOL 82 4 1 10 IPMI Support 82 4 1 10 1 Watchdogs 83 4 1 11 SMBIOS Support 83 4 1 12 LED Behavior During POST 84 4 1 13 BIOS Setup...

Page 5: ...ry Configuration 95 4 2 2 6 South Bridge Configuration 96 4 2 2 7 SMBIOS Event Log 97 4 2 3 Security Menu 98 4 2 4 Boot Menu 99 4 2 5 Save and Exit Menu 100 5 Functional Description 103 5 1 Block Diagram 103 5 2 Processor 104 5 3 Memory 105 5 3 1 DDR3 Main Memory 105 5 4 Network 105 5 5 I O Controller 105 5 6 Ethernet Ports 107 5 6 1 ATCA 3 0 Base Interface 107 5 6 2 Fabric Interface ATCA 3 1 107 ...

Page 6: ...figuration State 124 6 2 3 2 Exiting the Configuration State 124 6 2 3 3 Configuration Mode 125 6 2 3 4 Super I O Configuration Registers 125 6 2 4 UART1 and UART2 Register Map 131 6 2 4 1 UART Register Overview 131 6 2 5 UART Registers DLAB 0 132 6 2 5 1 Receiver Buffer Register 132 6 2 5 2 Transmitter Holding Register THR 132 6 2 5 3 Interrupt Enable Register IER 133 6 2 5 4 Interrupt Identifica...

Page 7: ...OS Reset Payload Request Register 159 6 3 12 6 Payload Reset Source for IPMC Register 160 6 3 12 7 Payload Reset Source for BIOS Register 160 6 3 12 8 Payload Reset Source for OS Register 161 6 3 12 9 IPMC Watchdog Timeout Register 163 6 3 12 10IPMC Watchdog Timeout for BIOS Register 163 6 3 12 11IPMC Watchdog Timeout for OS Register 164 6 3 12 12FPGA Payload Watchdog Threshold Register 164 6 3 12...

Page 8: ...7 Chassis Device Commands 184 8 1 7 1 System Boot Options Commands 185 8 1 8 Event Commands 195 8 1 9 LAN Device Commands 195 8 2 PICMG 3 0 Commands 196 8 3 Artesyn Embedded Technologies Specific Commands 198 8 3 1 Set Get Feature Configuration Commands 198 8 3 1 1 Set Feature Configuration Command 199 8 3 1 2 Get Feature Configuration Command 199 8 3 2 Serial Output Commands 200 8 3 2 1 Set Seria...

Page 9: ... 4 12 Enable Payload Control Command 219 8 4 13 Disable Payload Control Command 219 8 4 14 Reset IPMC Command 220 8 4 15 Hang IPMC Command 220 8 4 16 Graceful Reset Command 221 8 4 17 Get Payload Shutdown Time Out Command 222 8 4 18 Set Payload Shutdown Time Out Command 223 8 4 19 Get Module State Command 223 8 4 20 Enable Module Site Command 225 8 4 21 Disable Module Site Command 225 8 4 22 Reset...

Page 10: ... 242 10 1 3 3 IPMI Over LAN BASE 242 10 2 IPMC Upgrade 243 10 3 BIOS FPGA Update 244 10 4 Upgrade Package 245 A Troubleshooting 247 A 1 Error List 247 A 1 1 CPU Blade is Not Functioning Properly 247 B Related Documentation 249 B 1 Artesyn Embedded Technologies Embedded Computing Documentation 249 B 2 Related Specifications 249 ...

Page 11: ... J32 Pin Assignment 68 Table 3 10 Mezzanine Card Connector Signals 69 Table 3 11 Switch SW2 Settings 72 Table 3 12 Switch SW1 Setting 73 Table 3 13 Switch S7 Setting 73 Table 4 1 Network Boot Support Status 81 Table 4 2 Printout Floating Structure 85 Table 4 3 BIOS CLI Tool IPMIBPAR 86 Table 4 4 Primary Menu Description 87 Table 4 5 SCT Navigation Keys 88 Table 4 6 Main Menu Description 89 Table 4...

Page 12: ...r 126 Table 6 17 Global Super IO SERIRQ and Pre divide Control Register 127 Table 6 18 Logical Device Configuration Register Summary 127 Table 6 19 Logical Device Enable Register 128 Table 6 20 Logical Device Base IO Address MSB Register 128 Table 6 21 Logical Device Base IO Address LSB Register 128 Table 6 22 Logical Device Common Decode Ranges 129 Table 6 23 Logical Device Primary Interrupt Regi...

Page 13: ...k Register 156 Table 6 53 Reset Function Register 157 Table 6 54 IPMC Reset Payload Request Register 158 Table 6 55 BIOS Reset Payload Request Register 159 Table 6 56 OS Reset Payload Request Register 159 Table 6 57 Payload Reset Source for IPMC Register 160 Table 6 58 Payload Reset Source for BIOS Register 161 Table 6 59 Payload Reset Source for OS Register 162 Table 6 60 IPMC Watchdog Timeout Re...

Page 14: ...11 System Boot Options Parameter 98 188 Table 8 12 System Boot Options Parameter 100 Data Format 190 Table 8 13 System Boot Options Parameter 100 SET Command Usage 190 Table 8 14 System Boot Options Parameter 100 GET Command Usage 191 Table 8 15 System Boot Options Parameter 100 Supported Parameters 193 Table 8 16 boot_order Devices 194 Table 8 17 Supported Event Commands 195 Table 8 18 Supported ...

Page 15: ...unication Time Out Command Description 217 Table 8 45 Set Payload Communication Time Out Command Description 218 Table 8 46 Enable Payload Control Command Description 219 Table 8 47 Disable Payload Control Command Description 219 Table 8 48 Reset IPMC Command Description 220 Table 8 49 Hang IPMC Command Description 220 Table 8 50 Graceful Reset Command Description 221 Table 8 51 Get Payload Shutdo...

Page 16: ...ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 16 List of Tables ...

Page 17: ... Disk Module Connector Pinout 72 Figure 4 1 Main Menu 89 Figure 4 2 Advanced Menu 90 Figure 4 3 Security Menu 98 Figure 4 4 Boot Menu 99 Figure 4 5 Save and Exit Menu 100 Figure 5 1 Block Diagram 103 Figure 5 2 Intel Xeon Processor E5 2648L C604 Chipset Platform Overview 104 Figure 5 3 PCH Block Diagram 106 Figure 5 4 Overall SMBus Connections 111 Figure 6 1 Interrupt Structure on ATCA 7370 113 Fi...

Page 18: ...ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 18 List of Figures ...

Page 19: ...rdware accessories switch settings installation and removal procedures Controls Indicators and Connectors on page 61 describes external interfaces of the blade This includes connectors and LEDs BIOS on page 75 describes the features and setup of BIOS Functional Description on page 103 describes the functional blocks of the blade in detail This includes a block diagram description of the main compo...

Page 20: ...ion Code EDAC Error Detection and Correction EEPROM Electrically Erasable Programmable Read Only Memory EMC Electro magnetic Compatibility ESD Electro static Discharge FRU Field Replaceable Unit GPIO General Purpose Input Output I2C Inter Integrated Circuit Bus 2 wire serial bus and protocol I O Input Output ICH I O Control Hub also called South Bridge IMC Integrated Memory Controller IPMB Intelli...

Page 21: ...I Non maskable Interrupt NT Non transparent NVRAM Non volatile Random Access Memory OEM Original Equipment Manufacturer PCB Printed Circuit Board PCI E PCI Express PICMG PCI Industrial Computer Manufacturers Group PLL Phase Locked Loop POST Power on Self Test PP Payload Power RTC Real Time Clock Rx Receive line of a duplex serial communication interface SATA Serial AT Attachment high speed serial ...

Page 22: ...s digits are 0 through F for example used for addresses and offsets 0b0000 Same for binary numbers digits are 0 and 1 bold Used to emphasize a word Screen Usedforon screenoutputandcoderelatedelements or commands in body text Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File Exit Notation for s...

Page 23: ...nd 4 used in registers Logical OR Indicates a hazardous situation which if not avoided could result in death or serious injury Indicates a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message No danger encountered Pay attention to important information Notation Description ...

Page 24: ...Chapter 1 Introduction on page 37 Chapter 2 Hardware Preparation and Installation on page 45 Chapter 5 Functional Description on page 103 Figure 9 1 on page 227 6806800P54D August 2013 Updated Chapter 2 Hardware Preparation and Installation onpage45 Table2 1 andTable2 2 Added Figure 2 1 6806800P54E December 2013 Updated Safety Notes 6806800P54F June 2014 Re branded to Artesyn 6806800P54G September...

Page 25: ...ffice telecommunication industry and industrial control Only personnel trained by Artesyn or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equ...

Page 26: ...own expense The USB1 USB2 ports and the COM port are considered as debug maintenance ports During normal operation no cables must be connected to these ports Cables attached to these ports during maintenance must not exceed a length of 3m Installation Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching th...

Page 27: ...t the blade is bolted on the system and the system is shielded by enclosure Injuries or Short Circuits Blade or power supply In case the ORing diodes of the blade fail the blade may trigger a short circuit between input line A and input line B so that line A remains powered even if it is disconnected from the power supply circuit and vice versa To avoid damage or injuries always check that there i...

Page 28: ... the optical fibres against dirt and damage Dirt and damage can render the SFP module inoperable Only remove the optical plug when you are ready to connect a cable to the SFP module When no cable is connected cover the port with an optical port plug RJ 45 Connectors The RJ 45 connectors on the face plate must only be used for twisted pair Ethernet TPE and serial console connections according to fa...

Page 29: ...ecked and changed before blade installation Blade Damage Setting resetting the switches during operation can cause blade damage Therefore check and change switch settings before you install the blade Battery Blade Damage Wrong battery installation may result in hazardous explosion and blade damage Therefore always use the same type of Lithium battery as is installed and make sure the battery is in...

Page 30: ...ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Safety Notes 30 ...

Page 31: ...nen benötigen sollten wenden Sie sich bitte an die für Sie zuständige Geschäftsstelle von Artesyn Das System erfüllt die für die Industrie geforderten Sicherheitsvorschriften und darf ausschließlich für Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden Einbau Wartung und Betrieb dürfen nur von durch Artesyn ausgebildetem oder im Bereich El...

Page 32: ...tung kann im Wohnbereich Funkstörungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Maßnahmen durchzuführen Die nachfolgend aufgeführten Schnittstellen sind Wartungsschnittstellen USB1 USB2 und COM Während des Normalbetriebs darf an diesen Schnittstellen kein Kabel angeschlossen sein Im Wartungsfall angeschlossene Kabel dürfen eine Länge von 3m nicht überschreiten Inst...

Page 33: ...achten Sie deshalb die folgenden Hinweise Kennzeichnen Sie TPE Anschlüsse in der Nähe Ihres Arbeitsplatzes deutlich als Netzwerkanschlüsse Schließen Sie an TPE Buchsen ausschließlich SELV Kreise Sicherheitskleinspannungsstromkreise an Die Länge des mit dem Board verbundenen Twisted Pair Ethernet Kabels darf 100 m nicht überschreiten Betrieb Beschädigung des Blades Hohe Luftfeuchtigkeit und Kondens...

Page 34: ...n Die Installation und der Betrieb von SFP Modulen welche nicht zertifiziert sind und welche nicht den Sicherheitsstandards entsprechen kann Verletzungen zur Folge haben sowie zur Beschädigung des RTMs und von SFP Modulen führen Verwenden Sie daher nur SFP Module die zertifiziert sind und die den Sicherheitsstandards entsprechen Verletzungsgefahr Optische SFP Module können als Laserprodukte klassi...

Page 35: ...Schalter die nicht mit Reserved gekennzeichnet sind Prüfen und ändern Sie die Einstellungen der nicht mit Reserved gekennzeichneten Schalter bevor Sie das Blade installieren Beschädigung der Blade Das Verstellen von Schaltern während des laufenden Betriebes kann zur Beschädigung des Blades führen Prüfen und ändern Sie die Schaltereinstellungen bevor Sie das Blade installieren Batterie Beschädigung...

Page 36: ...ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G Sicherheitshinweise 36 ...

Page 37: ...es and is hot swap compatible based on the ATCA specification A single processor variant of the ATCA 7370 is also available It is called ATCA 7370 S The following are the main features of ATCA 7370 Form factor Single slot ATCA 280mm x 322mm Processor Intel Xeon E5 2648L eight core processor PCH chipset C604 chipset Memory Total of eight DDR3 DIMM slots supports up to 128 GB memory with speed rate ...

Page 38: ... The product is designed to meet the following standards Table 1 1 Standard Compliances Standard Description SN29500 8 Reliability requirements MIL HDBK 217F SR 332 TR NWT 000357 IEC 60068 2 1 2 3 13 14 Climatic environmental requirements The product can only be used in a restricted temperature range IEC 60068 2 27 32 35 Mechanical environmental requirements IEC 60950 1 EN 60950 1 UL CSA 60950 1 S...

Page 39: ...24 EN 300 386 v1 4 1 2008 FCC Part 15 Subpart B ICES 003 2004 VCCI V 3 2011 04 AS NZS CISPR22 2009 ANSI IPC A 610 Rev B Class 2 Manufacturing requirements ANSI IPC R 700B ANSI J 001 003 ISO 8601 Y2K compliance NEBS Standard GR 63 CORE NEBS level three Project is designed to support NEBS level three The compliance tests must be done with the customer target system NEBS Standard GR 1089 CORE Table 1...

Page 40: ...Introduction ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 40 Figure 1 1 Declaration of Conformity ...

Page 41: ...outtheblade smechanicaldata suchasdimensionsand weight Table 1 2 Mechanical Data Feature Value Dimensions width x height x depth Single slot ATCA 30mm x 351mm x 312mm 8U form factor Net weight 2930g without DIMMs 2496g with 4x 8GB DIMMs Weight including Artesyn standard packaging 4105 g without DIMMs 4318 g with 8x 8GB DIMMs ...

Page 42: ...ing graphics illustrate the mechanical layout of the blade Note On the single processor variant the processor and its DIMM sockets are populated on the upper side of the board Components associated with the second processor are not populated on this product variant Figure 1 2 Mechanical Layout S N Label ...

Page 43: ...vailable ATCA 7370 blade 5470 fit 182 815 hours RTM 7370 blade 950 fit 1 052 631 hours Standard for calculation SR332 Quality Level Quality Level II is most common Environment Typically Ground Fixed Controlled Assembly Ambient Temperature 40 o C Confidence Level 60 Table 1 3 Blade Variants Ordering Information Product Name Description ATCA 7370 ATCA BLADE DUAL INTEL XEON E5 2600 SERIES 8 CORE PROC...

Page 44: ...ct Identification The Figure 1 2 on page 42 shows the location of the serial number label ATCA 7370 ACCEL MOD Single coprocessor module to accelerate cryptography data compression and pattern matching Table 1 4 Blade Accessories Ordering Information continued Accessory Description ...

Page 45: ... the customer service 3 Remove the desiccant bag shipped together with the blade and dispose of it according to your country s legislation 2 2 Environmental and Power Requirements In order to meet the environmental requirements the blade has to be tested in the system in which it is to be installed Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage c...

Page 46: ... to 55 C 131 F exceptional operation according to NEBS Standard GR 63 CORE 40 C 40 F to 70 C 158 F may be further limited by installed accessories Temp Change 0 25 C min according to NEBS Standard GR 63 CORE 0 25 C min Rel Humidity 5 to 90 non condensing according to Artesyn internal environmental requirements 5 to 95 non condensing according to Artesyn internal environmental requirements Vibratio...

Page 47: ...the blade and not to the actual component temperature Blade Surface and Blade Damage High humidity and condensation on the blade surface causes short circuits Do not operate the blade outside the specified environmental limits Make sure the blade is completely dry and there is no moisture on any surface before applying power Blade Overheating and Blade Damage Operating the blade without forced air...

Page 48: ...06800P54G 48 1 Temperature Spot 1 on Power Entry Module Max 90 C exact location on top of the transformer 2 Temperature Spot 2 on 48V 12V DC DC Module Max 100 C exact location in the geometric middle of the heat spreader Figure 2 1 Location of Critical Temperature Spots Blade Top Side ...

Page 49: ... a TNV 2 or a safety extra low voltage SELV circuit A TNV 2 circuit is a circuit whose normal operating voltages exceed the limits for a SELV circuit under normal operating conditions and which is not subject to over voltages from telecommunication networks Table 2 2 Power Requirements Characteristic Value Rated Voltage Exception in the US and Canada 48 VDC to 60 VDC 48 VDC Operating Voltage Excep...

Page 50: ... 7370 module and with software simultaneously exercising as many functions and interfaces as possible This includes a particular load software provided by Intel designed to stress the processors to reach their theoretical maximum power specification Any difference in the system configuration or the software executed by the processors may affect the actual power dissipation Depending on the actual ...

Page 51: ...allation and Use 6806800P54G 51 2 3 Blade layout Note OnthesingleprocessorvarianttheprocessoranditsDIMMsocketsarepopulatedonthe upper side of the board Components associated with the second processor are not populated on this product variant Figure 2 2 Blade Layout ...

Page 52: ... for main memory DIMM modules You may install and or remove DIMM memory modules in order to adapt the main memory size to your needs The corresponding installation removal procedures are described in this section The location of the DIMM Memory Modules are shown in Figure Blade Layout on page 51 ATCA 7370 ATCA 7370 S supports low voltage DDR3 memory This is available upon request Damage of Circuit...

Page 53: ...plicable repeat steps 2 to 3 to install further modules Removal Procedure To remove a DIMM module 1 Remove blade from system as described in Installing and Removing the Blade on page 57 2 Open locks of socket at both sides The memory module is automatically lifted up 3 Remove module from socket 4 Repeat steps 2 to 3 in order to remove further memory modules Damage of Circuits Electrostatic dischar...

Page 54: ...70 ATCA 7370 S Installation and Use 6806800P54G 54 2 4 2 Cave Creek Module This section describes the steps to install remove the Cave Creek module The following figure illustrates the location of the Cave Creek module Figure 2 3 Cave Creek Module ...

Page 55: ...move the blade from the system as described in Installing and Removing the Blade on page 57 2 Align and fasten the four M2 5x 8mm standoffs from bottom side of Cave Creek module using the four M2 5x 4mm screws 3 Insert the Cave Creek module in the socket so that the module s standoffs fit in the blade s mounting holes Damage of Circuits Electrostatic discharge and incorrect module installation and...

Page 56: ...4mm screws 5 Reinstall the blade into the system as described in Installing and Removing the Blade on page 57 Cave Creek Module Removal To remove the Cave Creek module 1 Remove the blade from the system as described in Installing and Removing the Blade on page 57 2 Remove the four screws that holds the Cave Creek module Figure 2 4 Cave Creek Module Installation ...

Page 57: ...e installed in any AdvancedTCA node slot Do not install it in an AdvancedTCA hub slot 2 5 1 Installing the Blade To install the blade into an AdvancedTCA shelf proceed as follows Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten its life Before touching the blade or electronic components make sure that you are working in an ESD s...

Page 58: ... the shelf by placing the top and bottom edges of the blade in the card guides of the shelf Ensure that the guiding module of shelf and blade are aligned properly 3 Apply equal and steady pressure to the blade to carefully slide the blade into the shelf until you feel resistance Continue to gently push the blade until the blade connectors engage 4 Squeeze the lever and the latch together and hook ...

Page 59: ...eplate if applicable 2 5 2 Removing the Blade This section describes how to remove the blade from an AdvancedTCA system If an RTM is connected to the front blade make sure that the handles of both the RTM and the front blade are closed in order to power up the blade s payload Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten its ...

Page 60: ...handle from the faceplate Do not rotate the handle fully outward The blue LED blinks indicating that the blade power down process is ongoing 2 Wait until the blue LED is illuminated permanently then unlatch the upper handle and rotate both handles fully outward 3 Remove the faceplate cables if applicable 4 Rotate handle of the faceplate until the blade is detached from the shelf 5 Remove the blade...

Page 61: ...e possibility to cover unused faceplate elements like LEDs or push buttons behind a custom overlay foil 3 1 1 LEDs and Interfaces The blade s faceplate provides the following interfaces and control elements Two USB 2 0 ports Serial console port to connect to either payload or IPMC serial I F Out of Service In Service Attention User U1 U2 U3 LEDS and Hot Swap LEDs IPMC control Two Ethernet ports Re...

Page 62: ...Controls Indicators and Connectors ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 62 Figure 3 1 Faceplate LEDs ...

Page 63: ...rvice Red green controlled by IPMC If both red and green are lit it may look amber This LED is controlled by higher layer software such as middleware or applications Off after power up and lamp test finished Turned green ON by OS startup script or application Attention ATCA LED3 Amber Attention Amber This LED is controlled by higher layer software such as middleware or applications Off after power...

Page 64: ... 1 Faceplate Connectors Hot Swap Blue FRU State Machine During blade installation Blue Onboard IPMC powers up Blue blinking Blade is communicating with the shelf manager Off Blade is active During blade removal Blue blinking Blade is notifying the shelf manager that it is going to deactivate Blue Blade is ready to be extracted Table 3 1 Faceplate LEDs continued Indicator Color Description Table 3 ...

Page 65: ...ddress Bit 0 6 IPMC ISC PC1 Hardware Address Bit 1 7 IPMC ISC PC2 Hardware Address Bit 2 8 IPMC ISC PC3 Hardware Address Bit 3 9 IPMC ISC PD4 Hardware Address Bit 4 10 IPMC ISC PD5 Hardware Address Bit 5 11 IPMC ISC PD6 Hardware Address Bit 6 12 IPMC ISC PD7 Hardware Address Bit 7 13 IPMC IMC PD0 IPMB Clock Port A 14 IPMC IMC PD1 IPMB Data Port A 15 IPMC ISC PC5 IPMB Clock Port B 16 IPMC ISC PC4 I...

Page 66: ...ck CLK1A CLK1A CLK1B CLK1B CLK2A CLK2A 2 Update Channel SAS GE Redundancy UPD_P4_T X UPD_P4_T X UPD_P4_R X UPD_P4_R X 3 UPD_P2_T X UPD_P2_T X UPD_P2_R X UPD_P2_R X UPD_P3_T X UPD_P3_T X UPD_P3_R X UPD_P3_R X 4 UPD_GE_T X UPD_GE_ TX UPD_GE_ RX UPD_GE_R X UPD_P1_T X UPD_P1_T X UPD_P1_R X UPD_P1_R X 5 6 7 8 9 10 Table 3 6 Zone 2 Connector J23 Pin Assignment J23 Row Interface Col AB Col CD Col EF Col ...

Page 67: ... PCI E10_RN 2 PCI E10_TP 2 PCI E10_TN 2 PCI E10_RP 3 PCI E10_RN 3 PCI E10_TP 3 PCI E10_TN 3 8 PCI E CLOCK PCI E10_CLKP PCI E10_CLKN PCI E_RST NC NC NC NC NC 9 MISC IPMB_L_SCL IPMB_L_SDA V3P3_M PS0_N RTM_PB_N RTM_GRST_ N 10 V12P V12P V12P V12P NC RTM_EN_N SMB_CLK SMB_DAT Table 3 8 Zone 3 Connector J31 Pin Assignment J31 Row Interf ace Col AB Col CD Col EF Col GH 1 x16 PCIE from CPU1 PCIE_CPU1_ RX0 ...

Page 68: ...PCIE9_TN 0 PCIE9_RP 1 PCIE9_RN 1 PCIE9_TP 1 PCIE9_TN 1 2 PCIE9_RP 2 PCIE9_RN 2 PCIE9_TP 2 PCIE9_TN 2 PCIE9_RP 3 PCIE9_RN 3 PCIE9_TP 3 PCIE9_TN 3 3 PCIE Port8 PCIE8_RP 0 PCIE8_RN 0 PCIE8_TP 0 PCIE8_TN 0 PCIE8_RP 1 PCIE8_RN 1 PCIE8_TP 1 PCIE8_TN 1 4 PCIE8_RP 2 PCIE8_RN 2 PCIE8_TP 2 PCIE8_TN 2 PCIE8_RP 3 PCIE8_RN 3 PCIE8_TP 3 PCIE8_TN 3 5 PCIE Port7 PCIE7_RP 0 PCIE7_RN 0 PCIE7_TP 0 PCIE7_TN 0 PCIE7_R...

Page 69: ...Ie_TX0_N 5 PCIe_TX0_P 6 PCIe_RX1_N 6 PCIe_RX1_P 6 PCIe_RX0_N 6 PCIe_RX0_P 7 GND 7 GND 7 GND 7 GND 8 PCIe_TX3_N 8 PCIe_TX3_P 8 PCIe_TX2_N 8 PCIe_TX2_P 9 PCIe_RX3_N 9 PCIe_RX3_P 9 PCIe_RX2_N 9 PCIe_RX2_P 10 GND 10 GND 10 GND 10 GND 11 PCIe_TX5_N 11 PCIe_TX5_P 11 PCIe_TX4_N 11 PCIe_TX4_P 12 PCIe_RX5_N 12 PCIe_RX5_P 12 PCIe_RX4_N 12 PCIe_RX4_P 13 GND 13 GND 13 GND 13 GND 14 PCIe_TX7_N 14 PCIe_TX7_P 14...

Page 70: ...Use 6806800P54G 70 23 23 23 23 24 24 24 24 25 25 25 25 26 26 26 26 27 27 27 27 28 RESET_N 28 PRSNT_N 28 PWR_EN 28 PWR_GD 29 VCC12 29 VCC12 29 VCC3V3 29 VCC3V3 30 GND 30 GND 30 GND 30 GND Table 3 10 Mezzanine Card Connector Signals continued D Signal C Signal B Signal A Signal ...

Page 71: ...nd Use 6806800P54G 71 3 2 4 Onboard Connectors 3 2 4 1 TPM Head One TPM head is installed on the board and can be used for a Port 80 card for debug monitor It can also be reserved for a TPM module customization The head pin pitch is 2 54 mm Figure 3 2 TPM Connector Pinout ...

Page 72: ...board 3 3 Switch Settings Switches reside on the component side 1 of the board and are not covered by any other component Its pin 1 is clearly marked on the PCB and by default are OFF 3 3 1 PCH Switch Figure 3 3 USB 2 0 Flash Disk Module Connector Pinout Table 3 11 Switch SW2 Settings Switch PCH Function Default SW2 1 GPIO6 ON Load default BIOS setting OFF SW2 2 GPIO7 ON BIOS Crisis Recovery OFF ...

Page 73: ...inserted Note The S7 1 should also be ON in order to force the payload power on OFF SW1 2 No definition OFF SW1 3 No definition OFF SW1 4 No definition OFF Table 3 13 Switch S7 Setting Switch Function Default S7 1 ON Reset IPMC OFF IPMC operates normally Note when forcing board power on ordownloadingFPGAthroughcable the IPMC should be in reset state OFF S7 2 FPGA image flash BANK selection when us...

Page 74: ...Controls Indicators and Connectors ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 74 ...

Page 75: ...ible to select boot flash as device to boot from This is done via an IPMI command For further details refer Chapter 8 Supported IPMI Commands on page 181 The BIOS used on the blade is based on the Phoenix SecureCore Tiano SCT UEFI BIOS with several Artesyn extensions integrated Its main features are Initialize CPU chipset and memory Initialize PCI devices Setup utility for setting configuration da...

Page 76: ...settings Torestorethedefault values press F9 in Setup 4 1 1 Update and Recovery The ATCA 7370 has two different ways to update the BIOS Flash tool FCU and ipmitool in Linux Used for normal upgrade mode USB CD ROM or USB flash device This is used in BIOS recovery modes The BIOS contains online documentation which describes in detail the available menu options Therefore the description in this manua...

Page 77: ...old reset warm reset and S3 suspend resume The SMI routine is used to handle ECC error report on both the BIOS and OS The ECC error log is stored in the BIOS SPI Flash After Linux is booted up the Error Detection and Correction Module EDAC is also used to count the ECC error Correctable ECC Logging and Threshold setting in BIOS setup Advanced Menu Item Default Description Memory ECC Error Log Both...

Page 78: ... is described in the in chapter 7 13 of Intel Xeon Processor E5 1600 2400 2600 4600 Product Families System Agent BIOS Specification 1 01 document document number 489625 Artesyn recommends inserting memory modules of the same type into all slots of the ATCA 7370 With mixed memory like different model voltage or frequency the system may run in a degraded performance Though not recommended a certain...

Page 79: ...lizes them according to their resource requirements If the PCI s option ROM is detected it will be executed and its function implemented The network option ROM adds new boot option to the BIOS boot table The SAS option ROM shows SAS configuration utility menu which lets the end user create RAID volume 4 1 5 I O Device Configuration 4 1 5 1 Serial Ports The ATCA 7370 supports two serial ports in OS...

Page 80: ...t Interfaces If BIOS does not find any ready bootable device it will loop on the source list until a boot device becomes ready After 10 loops the BIOS initiates a cold reset and retries again or when configured the BMC watchdog bites BIOS organizes the devices in groups CD ROM HDD network floppy SAS HDD Any device can be set as the first boot device by raising it to the first boot device of its de...

Page 81: ...ow the SAS port physical number to assign sequence number For example BIOS and Linux will assign sequence number as following 4 1 6 2 Network Boot The BIOS contains a classic PXE Option ROM OpROMs The following table summarizes the network boot support status Physical port BIOS Linux P0 SAS0 sda P1 SAS1 sdb P2 SAS2 sdc P3 SAS3 sdd Table 4 1 Network Boot Support Status Ethernet Interface PXE Boot S...

Page 82: ...er where the console redirection is done The BIOS sets FPGA register 0x603 bit 0 to high Serial reduction control register to indicate the BIOS uses serial port 1 for SOL function The further steps to initialize SOL is done by IPMC 4 1 10 IPMI Support The ATCA 7370 BIOS provides the following IPMI support Checks if the IPMI controller is active If not it will display an appropriate error message R...

Page 83: ... on BIOS can disable BMC watchdog through the BIOS setup menu If BMC watchdog for BIOS is enabled it will be disabled when BIOS setup menu is invoked boot to shell or boot to OS Timer value for BIOS phases is also configurable through BIOS setup menu The default time value is set to three minutes and the BMC watchdog for BIOS phase is enabled by default The BIOS can disable the BMC watchdog for OS...

Page 84: ... 4 1 13 BIOS Setup Layout The BIOS Setup default is aligned with the ATCA 7370 BIOS defaults 4 1 13 1 Board Information Display The BIOS displays the following board related information in the BIOS setup under Board Info Current System label for the loaded BIOS defaults set BIOS version BIOS build date IPMI Firmware Version FPGA Version Onboard FPGA version BIOS Source boot flash device bank 4 1 1...

Page 85: ...ts the information contained in the Board Information to console 4 1 17 1 BIOS Printouts to DRAM BIOS console printouts are stored in a specific area of the DRAM The printouts are accessible by the OS allowing the use of the startup information for debugging and troubleshooting Storing the optional ROM printouts is not required All printouts from the serial console are logged into the DRAM buffer ...

Page 86: ... length of the floating pointer structure table in bytes Theversion1 00structureis14byteslong so this field contains 0Eh CHECKSUM 13 8 A checksum of the complete pointer structure All bytes specified by the length field including CHECKSUM and reserved bytes must add up to zero Table 4 2 Printout Floating Structure continued Field Offset in bytes bits Length in bits Description 40 00 I O addresses ...

Page 87: ...t menu To start the Setup utility press F2 key during the early stages of POST after the power up The following table briefly describes the Primary Menus options and most of the Primary Menus have sub menus s file Store IPMI Boot Parameter USER area read from file h Help Table 4 3 BIOS CLI Tool IPMIBPAR Option Description This functionality operates when the USB keyboard is enabled and through the...

Page 88: ...select a screen or menu For example Main screen Advanced screen Exit screen etc v Up Down The Up and Down Arrow keys allow to select an item or sub screen Plus Minu s The Plus and Minus keys allow to change the field value of a particular setup item For example Date and Time Tab The Tab key allows to select fields ESC The Esc key allows to discard any changes made and exit the SCT Setup When you a...

Page 89: ...u Description Field Description System Date Sets the time and date month day year format To change these values go to each field and enter the desired value Press the Tab key to move from hour to minute minute to second month to day or day to year There is no default value System Time System Information Gives the BIOS version CPU type memory type size etc ...

Page 90: ...rocessor Configuration Set CPU configuration See section Processor Configuration Peripheral Configuration Set system peripheral configuration See section Peripheral Configuration HDD Configuration Set hard drive and controller configuration See section HDD Configuration Memory Configuration Displays and provides options to change the memory settings See section Memory Configuration South Bridge Co...

Page 91: ...ions Warm Reset and Cold Reset Default is Warm Reset Warm Reset Counter Sets the default value of Warm Reset Counter Range 0 65535 Default is 5 RPB Terminal Type Emulation ANSI Extended ASCII char set VT100 ASCII char set VT100 Extends VT100 to support color function keys etc UTF8 Uses UTF8 encoding to map Unicode chars onto 1 or more bytes Options ANSI VT100 VT100 and UTF8 Default is VT100 RPB Ba...

Page 92: ...M Options Disabled and Enabled Default is Enabled Boot from USB Devices Enable or Disable booting from USB Devices Options Disabled and Enabled Default is Enabled BIOS Watchdog Enable or Disable BIOS POST Watchdog Options Disabled and Enabled Default is Enabled BIOS Watchdog Timeout Choose Timeout value for BIOS POST Watchdog Expiration value It is not available if the BIOS Watchdog is disabled Ra...

Page 93: ...and Enabled Default is Disabled CPU Flex Ratio Settings Allows for selecting the CPU Ratio value this value must be between Max efficiency ratio and Max non turbo ratio Range 12 30 If CPU Flex Ratio Override is disabled the CPU Flex Ratio Settings menu item is hidden To view this menu item set Advanced Processor Configuration CPU Flex Ratio Override to enable Default is 18 Enabled XD Enabled Execu...

Page 94: ... Disable Spread Spectrum Options Disabled and Enabled Default is Enabled RTM power policy Select RTM power policy Disable for RTM as an independent FRU or enable for RTM Activate Deactivate with front board Options Disabled and Enabled Default is Disabled Table 4 11 HDD Configuration Description Field Description SATA Interface Combination Select the SATA controllers operation mode Options IDE and...

Page 95: ...lect DDR Vdd voltage When DDR Vdd Limit is set to auto then based on the following conditions the memory voltage can be either 1 5V or 1 35V If all memory modules support 1 5V then the BIOS set memory voltage to 1 5V If all memory modules support 1 35V then the BIOS set memory voltage to 1 35V If some of the memory module support 1 35V and other support 1 5V then the BIOS set memory voltage to 1 5...

Page 96: ...Limit value if Runtime Error Logging option is enabled Range 1 65535 Default is 20 Table 4 12 Memory Configuration Description continued Field Description Table 4 13 South Bridge Configuration Description Field Description SB USB Config Set USB configuration See SB USB Configuration Table 4 14 SB USB Configuration Description Field Description USB1 Control Enable or disable Front Panel USB port 1 ...

Page 97: ...s Table 4 15 SMBIOS Event Log Description Field Description Event Log Enable or disable SMBIOS Event Log Option Disabled and Enabled Default is Enabled View SMBIOS event log View SMBIOS event log Mark SMBIOS events as read Mark SMBIOS events as read Marked SMBIOS events will not be displayed Clears SMBIOS events Clears SMBIOS events ...

Page 98: ...06800P54G 98 4 2 3 Security Menu Figure 4 3 shows the Security Menu options Figure 4 3 Security Menu Table 4 16 Security Menu Description Field Description Set Supervisor Password Set Setup Supervisor Password Set User Password Set Setup User Password ...

Page 99: ...ot Priority Order Sets the order of the devices group CD DVD Drive Sets the order of the CD DVD devices in CD DVD group FDD Drive Sets the order of the USB floppy drive devices in floppy group USB Drive Sets the order of the USB HDD devices in USB group SAS HDD Drive Sets the order of the SAS HDD devices in SAS HDD group SATA HDD Drive Sets the order of the SATA HDD devices in SATA HDD group ...

Page 100: ...twork Card group Internal Shell Sets the order of internal UEFI shell Table 4 17 Boot Menu Description continued Field Description Figure 4 5 Save and Exit Menu Table 4 18 Save and Exit Menu Description Field Description Exit Saving Changes This option is same as pressing F10 key Saves all changes of all menus then exits the setup configure driver The option finally resets the system automatically...

Page 101: ...re driver Finally resets the system automatically Load Setup Defaults This option is same as pressing F9 key Loads standard default values Discard Changes Loads the original value of the boot time but does not load the default setup value Save Changes Saves all changes of all menus but does not reset the system Table 4 18 Save and Exit Menu Description continued Field Description ...

Page 102: ...BIOS ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 102 ...

Page 103: ...PI IPMB A IPMB B 48V 48V COM1 2x USB SATA QPI Zone3 to RTM J30 Control Power COM2 COM2 1x USB 1x USB SANDY BRIDGE EP 0 SANDY BRIDGE EP 1 TPM DMI2 PCIe x8 Port3a b Reset Button Dual GbE T P0 1 optional PCIe x1 4x SAS 2 0 SPI 1000 Base T ATCA 7370 0GB Zone3 to RTM J31 Zone3 to RTM J32 Zone2 to Back plane J23 Zone2 to Back plane J20 Dual 1 10GbE X Fabric 2xUSB SPI 4 DDR3 VLP DIMM Slots 4 DDR3 VLP DIM...

Page 104: ...s 4 SSE4 The processor supports several Advanced Technologies Execute Disable Bit Intel 64 Technology Enhanced Intel SpeedStep Technology Intel Virtualization Technology and Simultaneous Multi Threading SMT The following figure shows the Intel Xeon E5 2648L processor block diagram Note On the single processor variant the processor and its DIMM sockets are populated on the upper side of the board C...

Page 105: ... channel resulting in a total of eight DDR3 DIMM sockets Supported DDR3 speeds are DDR3 800 DDR3 1066 DDR3 1333 and DDR3 1600 DDR3 signaling voltage level is 1 35 V 1 5 V Higher DDR3 memory speed may be supported by the next generation processor 5 4 Network 5 5 I O Controller Intel C604 chipset is PCH that is used with Intel Xeon E5 2648L Processor It provides the following interfaces x4 lane DMI ...

Page 106: ...l Description ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 106 The following figure shows the I O functions provided by C604 chipset and those used on ATCA 7370 ATCA 7370 S Figure 5 3 PCH Block Diagram ...

Page 107: ...ric Interface is provided by Intel 82599 Niantic It is in accordance to ATCA subsidiary specification 3 1 Ethernet for ATCA Systems Either two10GBase BX4 or two 1000Base BX Ethernet interfaces are connected to the fabric channel 1 and 2 in the Zone 2 providing support for ATCA 3 1 Option 1 and 9 Option 1 one 1000Base BX on Port 0 of the fabric channels 1 2 Option 9 one 10GBase BX4 on Port 0 3 of t...

Page 108: ... FW is stored in two independent memory images Crisis recovery control is provided to allow reboot of the IPMC from a second image if the upgraded FW image is corrupted FW images can be upgraded via HPM 1 IPMI using either IPMB or KCS interface The IPMC supports the initiation of a graceful shutdown of the host CPU The IPMC can force the CPU to reset It also controls the power and reset of the pay...

Page 109: ...ion and boot routines OS boot loaders and loaded OS The serial console of the payload CPU is available via SOL In addition to the SOL capability the serial console is also available on the blade faceplate using a RJ45 connector with Cisco pin out If a SOL session is established only the output is available on the faceplate Input is not possible during this time via the faceplate Alternatively to t...

Page 110: ...ormatted to contain IPMI request and response messages plus additional messages for discovery and authentication The IPMI over LAN functionality is supported at a level that allows the Serial over LAN feature to be implemented 5 13 USB 2 0 Interface The C604 chipset provides internal USB1 1 USB 2 0 host controllers with up to 14 USB2 0 ports Two ports are routed to the faceplate one port is routed...

Page 111: ...ons The following figure shows the overall SMBus connections on ATCA 7370 Note OnthesingleprocessorvarianttheprocessoranditsDIMMsocketsarepopulatedonthe upper side of the board Components associated with the second processor are not populated on this product variant Figure 5 4 Overall SMBus Connections ...

Page 112: ...reading IPMC can access the DIMM SPD for DIMM thermal information through mux control signal 5 15 Glue Logic FPGA The Glue Logic FPGA is a programmable logic device used for Power sequence control LPC interface under PCH for internal register access SPI Interface under IPMC for internal register and BIOS access Reset control logic Interruption control logic BIOS bank selection control Dual UART co...

Page 113: ...signal inputs The IO APIC device supports 24 interrupt sources In APIC mode the C604 chipset supports only Front side bus interrupt delivery not the serial APIC mode The following figure and tables summarize the interrupt sources and mappings for ATCA 7370 APIC mode is configured through BIOS after boot up phase which is done in legacy PIC mode The following diagram shows the interrupt signals con...

Page 114: ...PU0_DIMMS_HOT_N These thermal signals description please refer to chapter 15 Thermal Management These thermal can be arranged into FPGA register And when one signal is assert and isn t masked it can cause a interrupt to IPMC or PCH this feature can be reserved and some devices thermal management maybe be through acquire mode to read its thermal information such as LM75 Handle switch HDL_SW This si...

Page 115: ...Q3 via SERIRQ PIRQ 4 Serial Port B IRQ4 via SERIRQ PIRQ 5 Parallel Generic IRQ5 via SERIRQ PIRQ 6 Floppy IRQ6 via SERIRQ PIRQ 7 Parallel Generic IRQ7 via SERIRQ PIRQ Slave 8 Internal RTC Internal RTC Timer 1 HPET 9 Generic IRQ9 via SERIRQ SCI TCO or PIRQ 10 Generic IRQ10 via SERIRQ SCI TCO or PIRQ 11 Generic IRQ11 via SERIRQ SCI TCO or PIRQ or Timer 2 HPET 12 PS 2 Mouse IRQ12 via SERIRQ SCI TCO or...

Page 116: ...not shared with any other devices to guarantee the proper operation of Timer 2 The chipset does not prevent the sharing of IRQ11 Interrupts can individually be programmed to be edge or level except for IRQ0 IRQ2 IRQ8 and IRQ13 6 1 2 APIC D31 F0 Interrupt Mapping 14 SATA SATA Primary legacy mode or via SERIRQ or PIRQ 15 SATA SATA Secondary legacy mode or via SERIRQ or PIRQ Table 6 2 Non APIC PIC mo...

Page 117: ...internal devices see the chipset documentation 17 PIRQ B 18 PIRQ C 19 PIRQ D 20 PIRQ E GPIO Option for SCI TCO and HPET Timer For other internal devices see the chipset documentation 21 PIRQ F GPIO 22 PIRQ G GPIO 23 PIRQ H GPIO Table 6 3 APIC Mode Interrupt Mapping continued IRQ Interrupt Source Notes When programming the polarity of internal interrupt sources on the APIC interrupts 0 through 15 r...

Page 118: ...I interrupt through controlling the GPIO3 of PCH connect to FPGA Table 6 4 NMI Sources Cause of NMI Comment SERR goes active either internally externally using SERR signal or using message from processor Can instead be routed to generate an SCI through the NSI2SCI_EN bit Device 31 Function 0 TCO Base 08h Bit 11 IOCHK goes active using SERIRQ stream ISA System Error Can instead be routed to generat...

Page 119: ...timeout or when IPMC receives a command from shelf manager In Intel Xeon E5 2648L Processor either SMI or NMI interrupts can be enabled in MC_SMI_CNTRL register The type of interrupt trigger is based on the following conditions or scenarios A DIMM error counter exceeds the threshold Redundancy is lost on a mirrored configuration or A sparing operation completes Warm reset request This register is ...

Page 120: ...ciated MC_COR_ECC_CNT_X register Determine the time since the counter has been cleared If a spare channel exists and the threshold has been exceeded faster than would expected given the background rate of correctable errors sparing should be initiated The counter should be cleared to reset the overflow bit MC_RAS_STATUS REDUNDANC Y_LOSS 1 One channel of a mirrored pair had an uncorrectable error h...

Page 121: ...Read only w Write only r w Read and write w1c Write 1 to clear ignore bit while reading r w1c Read and write 1 to clear write 0 has no effect r w1s Read and write 1 to set write 0 has no effect r w1t Read and write 1 to toggle write 0 has no effect LPC The prefix LPC signals that the access is restricted to the LPC interface E g LPC r wmeansthat the register bit is read writable from the LPC inter...

Page 122: ...e LPC interface never responds to LPC Memory accesses 6 2 1 1 3 LPC Firmware Decoding The LPC interface never responds to LPC Firmware accesses Table 6 8 LPC I O Register Map Overview Base Address Address Size Address Range Name Description 0x4E 2 SIW Super IO Configuration Registers for Index and Date 0x80 1 POSTCODE POST Code Register BASE1 8 COM1 UART1 Serial Port 1 Logical Device 4 BASE1 addre...

Page 123: ...e FPGA provides and 8 bit wide register to store POST codes to the LPC I O address 0x80 The IPMC may read the POST code using the SPI interface with the signal BMC_SPI_S0_N asserted and the SPI address 0x7F Table 6 9 IPMC SPI Register SPI Address Range Address Range Name Description 0x00 0x7F REGISTERS FPGA Registers Table 6 10 POST Code Register LPC I O Address 0x80 IPMC SPI Address 0x7f Bit Desc...

Page 124: ...iguration State When the Super IO is not in the Configuration State reads return 0xFF and write data is ignored 6 2 3 1 Entering the Configuration State The device enters the Configuration State by the following contiguous sequence 1 Write 80H to Configuration Index Port 2 Write 86H to Configuration Index Port 6 2 3 2 Exiting the Configuration State The device exits the configuration state by the ...

Page 125: ...served registers may return non zero values Writes to reserved locations may cause system failure 6 2 3 4 1 Global Control Configuration Registers The Super IO Global Registers lie in the address range 0x00 0x2F All eight bits of the ADDRESS Port are used for register selection All non implemented registers and bits ignore writes and return zero when read The INDEX PORT is used to select a configu...

Page 126: ...erial Port 2 A write to this register selects the current logical device This allows access to the control and configuration registers for each logical device 0 LPC r w Table 6 15 Super IO Device Revision Register Index Address 0x21 Bit Description Default Access 7 0 Device Revision 0x01 LPC r Table 6 16 Super IO LPC Control Register Index Address 0x28 Bit Description Default Access 0 LPC Bus Wait...

Page 127: ...egister These registers are then accessed through the DATA PORT The Logical Device registers are accessible only when the device is in the Configuration state Table 6 17 Global Super IO SERIRQ and Pre divide Control Register Index Address 0x29 Bit Description Default Access 0 SERIRQ enable 0 disabled Serial interrupts disabled 1 enabled Logical devices participate in interrupt generations 0 LPC r ...

Page 128: ...The currently selected device is enabled 1 LPC r w 7 1 Reserved 0 LPC r Table 6 20 Logical Device Base IO Address MSB Register Index Address 0x60 Bit Description Default Access 7 0 Logical Device Base IO Address MSB 0 LPC r w Table 6 21 Logical Device Base IO Address LSB Register Index Address 0x61 Bit Description Default Access 2 0 Bits 0 to 2 are read only Decode is on 8 Byte boundary 0 LPC r 7 ...

Page 129: ...for Common Decode Ranges Table 6 22 Logical Device Common Decode Ranges IO Address range Description 0x3F8 0x3FF COM1 0x2F8 0x2FF COM2 0x2E8 0x2EF COM3 0x3E8 0x3EF COM4 Table 6 23 Logical Device Primary Interrupt Register Index Address 0x70 Bit Description Default Access 3 0 Interrupt level is used for Primary Interrupt 0x0 no interrupt selected 0x1 IRQ1 0x2 IRQ2 0x3 IRQ3 0x4 IRQ4 0x5 IRQ5 0x6 IRQ...

Page 130: ...RT IER and the occurrence of the corresponding UART event i e Modem Status Change Receiver Line Error Condition Transmit Data Request Receiver Data Available or Receiver Time Out and setting the OUT2 bit in the MCR Table 6 24 Logical Device 0x74 Reserved Register Index Address 0x74 Bit Description Default Access 7 0 Reserved 0x04 LPC r Table 6 25 Logical Device 0x75 Reserved Register Index Address...

Page 131: ...e set high by the system software to access the Baud Rate Generator Divisor Latches DLL and DLM Table 6 27 UART Register Overview LPC IO Address DLAB Bit value Description Base 0 Receiver Buffer RBR Read Only Base 0 Transmitter Holding THR Write Only Base 1 0 Interrupt Enable Register IER Base 2 X Interrupt Identification Register IIR Read Only Base 2 X FIFO Control Register FCR Write Only Base 3 ...

Page 132: ... the data byte at the top of the FIFO 6 2 5 2 Transmitter Holding Register THR This register holds the next data byte to be transmitted When the transmit shift register becomes empty the contents of the THR is loaded into the shift register The transmit data request TDRQ bit in the line status register is set to one Writing to THR while in FIFO mode puts THR to the top The data at the bottom of th...

Page 133: ...ed Table 6 30 Interrupt Enable Register IER if DLAB 0 LPC IO Address Base 1 Bit Description Default Access 0 Receive data interrupt enable disable 1 receive data interrupt enabled 0 receive data interrupt disabled 0 LPC r w 1 Transmitter holding register empty THRE interrupt enable disable 1 THRE interrupt enabled 0 THRE interrupt disabled 0 LPC r w 2 Receiver line status interrupt enable disable ...

Page 134: ...e trigger level was reached in non FIFO mode RBR has data 2 ReceiverTimeoutoccurred IthappensinFIFOmodeonly whenthereisdatainthe receive FIFO but no activity for a time period 3 Transmitter requests data In FIFO mode the transmit FIFO is half or more than half empty in non FIFO mode THR is read already 4 Modem Status one or more of the modem input signals has changed state Table 6 32 Interrupt Ide...

Page 135: ...Non FIFO mode Receive Buffer is full Non FIFO mode Reading the Receiver Buffer Register FIFO mode Trigger level was reached FIFO mode Reading bytes until Receiver FIFO drops below trigger level or setting RESETRF bit in FCR register 0b1100 Character Timeout indication FIFO Mode only At least 1 character is in receiver FIFO andtherewasnoactivityfora time period Reading the Receiver FIFO or setting ...

Page 136: ...tReady Ring Indicator Received Line Signal Detect Reading the modem status register Table 6 33 Interrupt Identification Register Decode continued Interrupt ID Interrupt Set Reset Function 3 0 Priority Type Source Reset Control Table 6 34 FIFO Control Register FCR LPC IO Address Base 2 Bit Description Default Access 0 FIFO enable disable 1 Transmitter and Receiver FIFO enabled 0 FIFO disabled 0 LPC...

Page 137: ...trol Register The read capability simplifies system programming and eliminates the need for separate storage in system memory 5 4 Reserved 0 LPC w 7 6 Receiver FIFO interrupt trigger level 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes 0 LPC w Table 6 34 FIFO Control Register FCR continued LPC IO Address Base 2 Bit Description Default Access Table 6 35 Line Control Register LCR LPC IO Address Base 3 ...

Page 138: ...an odd number of logic ones is selected 1 Even parity 0 Odd parity 0 LPC r w 5 Stick parity When bits 3 4 and 5 are set the parity bit is transmitted and checked as cleared When bits 3 and 5 are set and bit 4 is cleared the paritybitistransmittedandcheckedasset If bit 5 is cleared stick parity is disabled 1 Stick parity enabled 0 Stick parity disabled 0 LPC r w 6 Break control bit Bit 6 is set to ...

Page 139: ...cess to RBR THR and IER registers 0 LPC r w Table 6 35 Line Control Register LCR continued LPC IO Address Base 3 Bit Description Default Access Table 6 36 Modem Control Register MCR LPC IO Address Base 4 Bit Description Default Access 0 Data terminal ready DTR output control 1 DTR output in low active state 0 DTR output in high state 0 LPC r w 1 Request to send RTS output control 1 RTS output in l...

Page 140: ... read and a new character is now at the top of the FIFO Bitsonethroughfouraretheerrorconditionsthatproduceareceiverlinestatusinterruptwhen any of the corresponding conditions are detected and the interrupt is enabled These bits are not cleared by reading the erroneous byte from the FIFO or receive buffer 4 Local loop back diagnostic control When loop back is activated Transmitter TXD is set high R...

Page 141: ...ved and transferred into the RBR or the FIFO DR is cleared by reading all of the data in the RBR or the FIFO 1 New data received 0 No new data 0 LPC r 1 Overrun error OE indicator When OE is set it indicates that before the character in the RBR was read it was overwritten by the next character transferred into the register OE is cleared every time the CPU reads the contents of the LSR If the FIFO ...

Page 142: ...C r 3 Framing Error FE indicator When FE is set it indicates that the received character did not have a valid set stop bit FE is cleared every time the CPU reads the contents of the LSR In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the CPU when its associated character is at the top of the FIFO The ACE tries to res...

Page 143: ...aracter transfer is enabled after RXD goes to the marking state for at least two Receiver CLK samples and then receives the next valid start bit 1 Full WORD transmission time exceeded 0 Normal operation 0 LPC r 5 Transmit Holding Register Empty THRE indicator THRE is set when the THR is empty indicating that the ACE is ready to accept a new character If the THRE interrupt is enabled when THRE is s...

Page 144: ...ransmitter Empty TEMT indicator TEMT bit is set when the THR and the TSR are both empty When either the THR or the TSR contains a data character TEMT is cleared In the FIFO mode TEMT is set when the transmitter FIFO and shift register are both empty 1 THR Transmit FIFO TSR empty 0 THR Transmit FIFO TSR contains data 1 LPC r 7 FIFO data error In the FIFO mode LSR7 is set when there is at leastonepa...

Page 145: ...utoflow control is enabled DCTS is cleared no interrupt is generated 1 Change in state of CTS input since last read 0 No change in state of CTS input since last read 0 LPC r w 1 Change in data set ready DDSR indicator DDSR indicates that the DSR input has changed state since the last time it was read by the CPU When DDSR is set and the modemstatusinterruptisenabled amodem status interrupt is gener...

Page 146: ...stic test mode LOOP MCR4 1 this bit is equal to the MCR bit 1 RTS Ext LPC r 5 Complement of the data set ready DSR input When the ACE is in the diagnostic test mode LOOP MCR4 1 this bit is equal to the MCR bit 0 DTR Ext LPC r 6 Complement of the ring indicator RI input When the ACE is in the diagnostic test mode LOOP MCR4 1 this bit is equal to the MCR bit 2 OUT1 Not supported Ext LPC r 7 Compleme...

Page 147: ... loaded with 0 the 16X output clock is stopped Upon loading either of the Divisor latches a 16 bit baud counter is immediately loaded This prevents long counts oninitial load Access to the Divisor latch can be done with a word write The UART_CLK is the CLK_UART 48MHz input divided by the pre divider set by the Super IO Configuration Register Offset 0x29 The baud rate of the data shifted in out of ...

Page 148: ...ccess use the base address 0x600 and add the Address Offset An LPC I O write access to an address not listed in this table or marked with a in the LPC I O column is ignored A corresponding read access delivers always zero Note LPC I O Address 0x600 Address Offset Table 6 40 Divisor Latch LSB Register DLL if DLAB 1 LPC IO Address Base Bit Description Default Access 7 0 Divisor Latch LSB DLL Undef L...

Page 149: ...ersion Register 0x02 Reserved 0x03 rw r Serial Redirection Control Register 0x04 r rw Serial over LAN SOL Control Register 0x05 r rw Serial Routing Register 0x06 r rw IPMC Power Level Register 0x07 rw Payload Power Control Register 0x08 rw rw I2C Switch Control Register 0x09 rw Payload Power button Register 0x0A 0E Reserved 0x0F rw rw Reset Mask Register 0x10 rw rw Reset Function Register 0x11 w I...

Page 150: ...Registers 0x33 36 rw HFI Mode Reset Control Registers 0x37 3F Reserved 0x40 r rw Flash Control Register 0x41 48 Reserved 0x49 r rw IPMC Scratch Register 0 0x4A r rw RTM Status and Control Register 0x4B 55 Reserved 0x56 r rw Blue LED Status and Control Register 0x57 rw r User LED Status and Control Register 0x58 r r MISC Status and Control Register 0x59 r r Debug Switch and LED Status Register 0x5A...

Page 151: ... PCA9555 2 Registers 0x6C 6F rw PCA9555 3 Registers 0x70 73 rw PCA9555 4 Registers 0x74 75 r r Thermal Event Registers 0 1 0x76 7D rw r LPC Scratch Registers 0 7 0x7E r rw IPMC Scratch Register 1 0x7F r r POST Code Register Table 6 42 FPGA Register Map Overview continued Address Offset 1 LPC I O IPMC SPI Description 1 For LPC I O access add the LPC I O Base Address 0x600 Table 6 43 Module Identifi...

Page 152: ...route the corresponding port serial IPMC interface in case of serial over lan SOL Table 6 44 Version Register Address Offset 0x01 Bit Description Default Access 7 0 Specifies FPGA version r BIOS should never set both status bits Table 6 45 Serial Redirection Control Register Address Offset 0x03 Bit Description Default Access 0 COM1 used for serial redirection 0 COM1 not used for serial redirection...

Page 153: ... SOL Control Register Address Offset 0x04 Bit Description Default Access 0 SOL over COM1 enable 0 disabled 1 enabled COM1 is forwarded to IMPC 0 IPMC r w LPC r 1 SOL over COM2 enable 0 disabled 1 enabled COM2 is forwarded to IMPC 0 IPMC r w LPC r 7 2 Reserved 0 r Table 6 47 Serial Routing Register Address Offset 0x05 Bit Description Default Access 1 0 00 COM1 to Faceplate and COM2 to RTM 01 COM1 t...

Page 154: ...bit1 in this register is 0 FPGA_COM_SW outputs high level When it is in 1 it outputs to low level Table 6 48 IPMC Power Level Register Address Offset 0x06 Bit Description Default Access 7 0 IPMC Power Level IPMC writes a value which represents a defined power level 0x00 IPMC r w LPC r Whenever the IPMC writes and data into this register it should also produce an 8 ms negative pulse on FPGA_PCH_GPI...

Page 155: ...ol Register Address Offset 0x07 Bit Description Default Access 0 IPMC turn on payload power request 1 Payload power on 0 Payload power off 0 IPMC r w 7 1 Reserved 0 r Table 6 50 I2C Switch Control Register Address Offset 0x08 Bit Description Default Access 0 FPGA_SPD_MUX_S 0 0 IPMC r w LPC r 1 FPGA_SPD_MUX_S 1 1 IPMC r LPC r w 2 FPGA_PCH_I2C_SEL 0 IPMC r w LPC r 7 3 Reserved 0 r ...

Page 156: ...sserted ThisregistercanbereadorwrittenbythehostCPU A one in the register bit indicates that the associated reset is enabled A zero indicates that the associated reset source is masked Table 6 51 Payload Power Button Register Address Offset 0x09 Bit Description Default Access 0 FPGA_PCH_PWRBTN_N 1 IPMC r w 7 1 Reserved 0 r Table 6 52 Reset Mask Register Address Offset 0x0F Bit Description Default A...

Page 157: ...sabled 0 LPC r w IPMC r 5 Enable FPGA Watchdog reset payload 1 enabled 0 disabled 0 LPC r w IPMC r 6 Enable BIOS reset payload 1 enabled 0 disabled 0 LPC r w IPMC r 7 Enable OS reset payload 1 enabled 0 disabled 0 LPC r w IPMC r Table 6 52 Reset Mask Register continued Address Offset 0x0F Bit Description Default Access Table 6 53 Reset Function Register Address Offset 0x10 Bit Description Default ...

Page 158: ...lect the function of RTM push button reset payload request 1 Warm reset 0 Cold reset 1 LPC r w IPMC r 5 Select the function of FPGA watchdog reset 1 Warm reset 0 Cold reset 1 LPC r w IPMC r 6 Select the function of BIOS reset payload request 1 Warm reset 0 Cold reset 1 LPC r w IPMC r 7 Select the function of OS reset payload request 1 Warm reset 0 Cold reset 1 LPC r w IPMC r Table 6 53 Reset Funct...

Page 159: ...set Payload Request Register The OS software writes 0x5A to this address and launches a payload reset request If the related bit in Reset Mask Register is high a warm o cold reset will occur based on the reset function register bit Table 6 55 BIOS Reset Payload Request Register Address Offset 0x12 Bit Description Default Access 7 0 Writing magic word 0xA5 will cause a reset request LPC w Table 6 5...

Page 160: ...it indicates that the associated reset has occurred If more than one reset occurs from different sources without clearing the corresponding register bits one can not determine the most recent reset source since more than one bit will be set The same situation will happen if two reset sources go active at the same time Table 6 57 Payload Reset Source for IPMC Register Address Offset 0x14 Bit Descri...

Page 161: ...he most recent reset source since more than one bit will be set The same situation will happen if two reset sources go active at the same time Table 6 58 Payload Reset Source for BIOS Register Address Offset 0x15 Bit Description Default Access 0 Payload Power on reset 1 Reset occurred RST_N 1 LPC r w1c 1 Reserved 0 LPC r w1c 2 Front board push button reset payload request 1 Reset occurred 0 LPC r ...

Page 162: ...set 1 Reset occurred RST_N 1 LPC r w1c 1 Reserved 0 LPC r w1c 2 Front board push button reset payload request 1 Reset occurred 0 LPC r w1c 3 IPMC reset payload request 1 Reset occurred 0 LPC r w1c 4 RTM push button reset payload request 1 Reset occurred 0 LPC r w1c 5 FPGA Watchdog reset payload request 1 Reset occurred 0 LPC r w1c 6 BIOS reset payload request 1 Reset occurred 0 LPC r w1c 7 OS rese...

Page 163: ...lear certain bits by writing 1 to it This register is only used for communication between the IPMC and the BIOS software FPGA will not use these bits by itself OS should never write to this register Table 6 60 IPMC Watchdog Timeout Register Address Offset 0x17 Bit Description Default Access 0 IPMC Watchdog Timeout 0 No IPMC Watchdog Timeout 1 IPMC Watchdog Timeout occurred 0 IPMC r w 1 IPMC Watchd...

Page 164: ...6 bit internal watchdog reserved for future payload use Unit is one msec with a maximum time of 65535 ms When 0 is written into it the watchdog will be disabled and never bite Address Offset Table 6 62 IPMC Watchdog Timeout for OS Register Address Offset 0x19 Bit Description Default Access 0 IPMC Watchdog Timeout 1 IPMC Watchdog Timeout occurred 0 LPC r w1c 1 IPMC Watchdog Pre Timeout 1 IPMC Watch...

Page 165: ...e time set by this register the latter will issue a cold reset to the former Payload will not be affected by the reset of the IPMC The IPMC software writes this register to set the timeout threshold of the FPGA IPMC Watchdog Unit is one second maximum time is 255s When 0 is written to it the watchdog will be disabled and will never bite Writing and other data will enable and restart the FPGA IPMC ...

Page 166: ...1 DEF_SPI_WP_N output low 0 LPC r IPMC r w 1 Inverted of REC_SPI_WP_N output 0 REC_SPI_WP_N output high 1 REC_SPI_WP_N output low 0 LPC r IPMC r w 6 2 Reserved 00000 r 7 Payload Boot SPI Flash select 0 Default Boot Flash linked to PCH Recovery one to IPMC 1 Recovery Boot Flash linked to PCH Default one to IPMC 0 LPC r IPMC r w Table 6 67 RTM Status and Control Register Address Offset 0x4A Bit Desc...

Page 167: ...ontinued Address Offset 0x4A Bit Description Default Access Table 6 68 User LED Status and Control Register Address Offset 0x56 Bit Description Default Access 1 0 Software set Blue LED mode 00 Solid on 01 Long blinking 10 Short blinking 11 Off 00 LPC r IPMC r w 2 Blue LED master selection 0 Software control Blue LED with bit1 0 setting in this register 1 FPGAcontrolBlueLEDaccordingtohandle status ...

Page 168: ...MC r 1 Control user LED 3 red color output Signal LED_USER3_RED_N 0 LED_USER3_RED_N is driven high 1 LED_USER3_RED_N is driven low 0 LPC r w IPMC r 2 Control user LED 1 red color output Signal LED_USER1_RED_N 0 LED_USER1_RED_N is driven high 1 LED_USER1_RED_N is driven low 0 LPC r w IPMC r 3 Control user LED 2 red color output Signal LED_USER2_RED_N 0 LED_USER2_RED_N is driven high 1 LED_USER2_RED...

Page 169: ...6 70 Miscellaneous Status and Control Register Address Offset 0x58 Bit Description Default Access 0 FRB_HDL_SW_N Ext r 1 BMC_WDO_N Ext r 3 2 CPU_SKTOCC_N 1 0 Ext r 4 CPU_IVY_N Ext r 5 PCH_HOT_N Ext r 6 Reserved 0 r 7 IPMC to payload NMI request 1 NMI active 0 NMI inactive Note FPGA_PCH GPIO3 signal will also be controlled by warm reset procedure 0 IPMC r w LPC r Table 6 71 Debug Switch and LED Sta...

Page 170: ... seven segment LED displays which can be read by IPMC at SPI address 0x7F 6 4 Standard Status Codes Table 6 72 LPC Scratch Registers Address Offset 0x76 7D Bit Description Default Access 7 0 LPC Scratch bits 0x00 LPC r w IPMC r Table 6 73 POST Code Register Address Offset 0x7F Bit Description Default Access 7 0 POST codes from host 0x00 IPMC r Table 6 74 Component Status Codes Status Code Code Sym...

Page 171: ...x2E POSTCODE_CC_DIAGNOSTIC_SUMMARY 0x2F POSTCODE_CC_SMBIOS 0x30 POSTCODE_CC_SMM_COMMUNICATION 0x31 POSTCODE_CC_SMM_RUNTIME 0x32 POSTCODE_CC_SMM_SERVICES 0x33 POSTCODE_CC_FIRMWARE_DEVICE 0x34 POSTCODE_CC_CAPSULE_SERVICES 0x35 POSTCODE_CC_MONOTONIC_COUNTER 0x36 POSTCODE_CC_SMBIOS_EVENT_LOG 0x37 POSTCODE_CC_RTC 0x38 POSTCODE_CC_BOOT_MANAGER 0x39 POSTCODE_CC_VGA 0x3A POSTCODE_CC_HII_FORMS_BROWSER 0x3B...

Page 172: ...CI 0x49 POSTCODE_CC_XHCI 0x4A POSTCODE_CC_UHCI 0x4B POSTCODE_CC_OHCI 0x4C POSTCODE_CC_USB_KEYBOARD 0x4D POSTCODE_CC_USB_MOUSE 0x4E POSTCODE_CC_USB_MASS_STORAGE 0x4F POSTCODE_CC_CONSOLE_SPLITTER 0x50 POSTCODE_CC_GRAPHICS_CONSOLE 0x51 POSTCODE_CC_SERIAL_CONSOLE 0x52 POSTCODE_CC_TEXT_CONSOLE 0x53 POSTCODE_CC_DISK_IO 0x54 POSTCODE_CC_PARTITION 0x55 POSTCODE_CC_SETUP 0x56 POSTCODE_CC_LEGACY_BIOS 0x57 P...

Page 173: ...OSTCODE_CC_PCH 0xC4 POSTCODE_CC_SATA 0xD1 POSTCODE_CC_FLASH_CONTROLLER 0xD2 POSTCODE_CC_FLASH_DEVICE 0xD3 POSTCODE_CC_FINGERPRINT_SENSOR 0xD4 POSTCODE_CC_CLOCK_CONTROLLER 0xD5 POSTCODE_CC_EMBEDDED_CONTROLLER 0xD6 POSTCODE_CC_SERIAL_CONTROLLER Table 6 75 Progress Status Codes Status Code Code Symbol 0x01 POSTCODE_PC_COMP_PEI_BEGIN 0x02 POSTCODE_PC_COMP_PEI_END 0x03 POSTCODE_PC_COMP_DXE_BEGIN 0x04 P...

Page 174: ... POSTCODE_PC_SEC_ENTRY 0xE1 POSTCODE_PC_SEC_EXIT 0xE2 POSTCODE_PC_PEI_ENTRY 0xE3 POSTCODE_PC_PEI_EXIT 0xE4 POSTCODE_PC_IPL_DXE 0xE5 POSTCODE_PC_IPL_S3 0xE6 POSTCODE_PC_S3_OS 0xE7 POSTCODE_PC_IPL_RECOVERY 0xE8 POSTCODE_PC_IPL_EXIT 0xE9 POSTCODE_PC_DXE_ENTRY 0xEA POSTCODE_PC_DXE_EXIT 0xEB POSTCODE_EC_PEI_MEMORY 0xEC POSTCODE_EC_PEI_IPL 0xED POSTCODE_EC_IPL_DXE 0xEE POSTCODE_EC_IPL_PPI 0xEF POSTCODE_...

Page 175: ...able on the base interface The sideband interface of the Intel 350 in pass through mode is used to transmit receive its terminal characters via the base interface You can configure the SOL parameters using the standard IPMI commands or via an open source tool called ipmitool 7 2 Installing the ipmitool You can download the open source tool ipmitool from http ipmitool sourceforge net at the time of...

Page 176: ...ring SOL Parameters You can configure the following SOL parameters You can use standard IPMI commands or the ipmitool to modify the parameters 7 3 1 Using Standard IPMI Commands This example shows how to set up the SOL configuration parameter with standard IPMI commands Ipmicmd is used on the local IPMC and the IP is configured Table 7 1 SOL Parameters Parameter Description Set LAN Configuration P...

Page 177: ...on Parameter Set In Progress Commit ipmicmd k f 0 c 1 1 0 2 smi 0 7 3 2 Using ipmitool The example below shows how to setup a LAN configuration parameter for a potential SOL session with ipmitool for base 1 channel 1 n0s70 ipmitool lan set 1 ipaddr 172 16 0 221 Setting LAN IP Address to 172 16 0 221 n0s70 The following example shows how to query the LAN parameters that are currently in use for a p...

Page 178: ... 0 1 Default Gateway MAC 00 00 00 00 00 00 RMCP Cipher Suites 1 2 3 3 Cipher Suite Priv Max Not Available root localhost ipmitool lan print 2 Set in Progress Set Complete Auth Type Support Auth Type Enable Callback User Operator Admin OEM IP Address Source Unspecified IP Address 172 17 1 220 Subnet Mask 255 255 0 0 MAC Address 00 00 00 00 00 00 Default Gateway IP 172 17 0 1 Default Gateway MAC 00 ...

Page 179: ...s detailed above are fulfilled 2 Compile and install the ipmitool on your target which is destined for opening the SOL session on the ATCA 7370 For details refer to Installing the ipmitool on page 175 3 Apply an IP address to the ATCA 7370 SOL interface For details refer to Configuring SOL Parameters on page 176 4 If necessary change user and password Default user is soluser and password is solpas...

Page 180: ...he ATCA 7370 SOL interface ipmitool C 1 I lanplus H 172 16 0 221 U soluser P solpasswd k gkey sol activate For details on the command parameters refer to the ipmitool documentation available on http ipmitool sourceforge net To access BIOS setup screen it is necessary to reset the payload SOL session is only available if the payload is powered on and initialized by the BIOS ...

Page 181: ...ing IPMI commands to support the system messaging interfaces Table 8 1 Supported Global IPMI Commands Command NetFn Request Response CMD Get Device ID 0x06 0x07 0x01 Cold Reset 0x06 0x07 0x02 Warm Reset 0x06 0x07 0x03 Get Self Test Results 0x06 0x07 0x04 Get Device GUID 0x06 0x07 0x08 Table 8 2 Supported System Interface Commands Command NetFn Request Response CMD Set BMC Global Enables 0x06 0x07 ...

Page 182: ...s 0x06 0x07 0x43 Get User Access 0x06 0x07 0x44 Set User Name 0x06 0x07 0x45 Get User Name 0x06 0x07 0x46 Set User Password 0x06 0x07 0x47 Set User Payload Access 0x06 0x07 0x4C Get User Payload Access 0x06 0x07 0x4D Master Write Read 0x06 0x07 0x52 Set Channel Security Keys 0x06 0x07 0x56 Table 8 2 Supported System Interface Commands continued Command NetFn Request Response CMD Table 8 3 Supporte...

Page 183: ...Request Response CMD Get SEL Info 0x0A 0x0B 0x40 Reserve SEL 0x0A 0x0B 0x42 Get SEL Entry 0x0A 0x0B 0x43 Add SEL Entry 0x0A 0x0B 0x44 Clear SEL 0x0A 0x0B 0x47 Get SEL Time 0x0A 0x0B 0x48 Set SEL Time 0x0A 0x0B 0x49 Table 8 5 Supported FRU Inventory Commands Command NetFn Request Response CMD Get FRU Inventory Area Info 0x0A 0x0B 0x10 Read FRU Data 0x0A 0x0B 0x11 Write FRU Data 0x0A 0x0B 0x12 ...

Page 184: ...ading Factors 0x04 0x05 0x23 Set Sensor Hysteresis 0x04 0x05 0x24 Get Sensor Hysteresis 0x04 0x05 0x25 Set Sensor Threshold 0x04 0x05 0x26 Get Sensor Threshold 0x04 0x05 0x27 Set Sensor Event Enable 0x04 0x05 0x28 Get Sensor Event Enable 0x04 0x05 0x29 Get Sensor Event Status 0x04 0x05 0x2B Get Sensor Reading 0x04 0x05 0x2D Get Sensor Type 0x04 0x05 0x2F Table 8 7 Supported Chassis Device Commands...

Page 185: ...ters 96to127areOEM specific When using the Get Set System Boot Options command with parameter selector of 96 97 98 the Set Selector and the Block Selector should be set to 0x00 When using the Get Set System Boot Options command with parameter selector of 100 the Set Selector and the Block Selector have a specific meaning Details are given in System Boot Options Parameter 100 on page 188 for detail...

Page 186: ...oaded into the FPGA at the next power cycle of the payload Bit 0 Default backup boot flash selection 0 Boot from default boot flash 1 Boot from backup boot flash Note the newly selected boot flash is connected to the payload immediately which means writing to the flash is possible Its image is executed after the next power up or cold reset of the payload The System Boot Options parameter 96 is non...

Page 187: ...fic OEM parameter Table 8 10 System Boot Options Parameter 97 Data Byte Description 1 POST Type Data 1 Set Selector This is the processor ID for which the boot option is to be set 2 Data 2 POST Type Selector This parameter is used to specify the POST type that the IPMC will execute 0x00 Short POST 0x01 Long POST 0x02 to 0xFF Not used The System Boot Options parameter 97 is non volatile It survives...

Page 188: ...gured using this parameter are typically a subset of the boot options which you can configure in the boot firmware directly for example using a setup menu TheIPMCcontainsastorageareaforthepayloadbootoptions Whenthebladeboots theboot firmware reads out these boot options from the IPMC interprets them and executes the boot process accordingly Note that the boot options stored in the IPMC have higher...

Page 189: ...d is used to rollback the user area in case of mis configuration To load the default settings can be done typically by an on board switch to clear the CMOS The number of boot options stored in the IPMC may differ from project to project The following figure explains the basic information flow related to the system boot options parameter 100 Changing a boot option in the firmware setup menu changes...

Page 190: ...options LSB first The number of bytes must be calculated and written into this field by the software which writes boot options into the storage area The values of 0x0000 and 0xFFFF indicate that no valid data in the storage area 2 n Boot options The boot options are stored in the form of ASCII texts with the following format name value where all name value pairs are separated by one zero byte The ...

Page 191: ...rea is locked by another software entity 82h illegal write access Table 8 14 System Boot Options Parameter 100 GET Command Usage Byte Description Request Data 1 Parameter Selector 7 reserved 6 0 parameter selector must be 100 2 Set Selector 0h user area 1h default area All other values are reserved 3 Block Selector Offset into the storage area of the boot options in multiples of 16 bytes Response ...

Page 192: ...e area a series of read commands can be issued with the block selector in 1 increment Once the error code C9 is returned the limit has been reached and the total available space of the storage area can be determined by the block selector of the last issued command This is supported by HPI for details refer to the System Management Interface Based on HPI B User s Guide related to your system enviro...

Page 193: ...off off basenet_boot on off on artm_sas_boot on off on usb_boot on off on bios_wdt on off on bios_wdt_timeout numeric 180 6000 180 os_boot_wdt on off on os_boot_wdt_timeout numeric 180 6000 2400 en_cmp all 1 2 3 4 5 6 7 all en_ht on off on flexratio on off off ratio_value numeric 12 30 18 en_xd on off off virtualization on off on speedstep on off on turbo_mode on off off c_states on off on vtd_sup...

Page 194: ...d boot_option_3 usb1 usb2 usbartm boot_option_4 basenet0 basenet1 boot_option_5 sashdd boot_option_6 frontnet0 frontnet1 Table 8 16 boot_order Devices Device Description sashdd SAS HDD mounted on the RTM frontnet Front Panel Network basenet0 Base0 Network basenet1 Base1 Network usb1 USB frontpanel 1 usb2 USB frontpanel 2 usbartm USB artm usbcdrom USB cdrom usbfdd USB floppy disk efishell Built in ...

Page 195: ...quest Response CMD Set Event Receiver 0x04 0x05 0x00 Get Event Receiver 0x04 0x05 0x01 Platform Event 0x04 0x05 0x02 Table 8 18 Supported LAN Device Commands Command NetFn Request Response CMD Set LAN Configuration Parameters 0x0C 0x0D 0x01 Get LAN Configuration Parameters 0x0C 0x0D 0x02 Set SOL Configuration Parameters 0x0C 0x0D 0x21 Get SOL Configuration Parameters 0x0C 0x0D 0x22 ...

Page 196: ...l 0x2C 0x2D 0x04 Get FRU LED Properties 0x2C 0x2D 0x05 Get FRU LED Color Capabilities 0x2C 0x2D 0x06 Set FRU LED State 0x2C 0x2D 0x07 Get FRU LED State 0x2C 0x2D 0x08 Set IPMB State 0x2C 0x2D 0x09 Set FRU Activation Policy 0x2C 0x2D 0x0A Get FRU Activation Policy 0x2C 0x2D 0x0B Set FRU Activation 0x2C 0x2D 0x0C Get Device Locator Record ID 0x2C 0x2D 0x0D Set Port State 0x2C 0x2D 0x0E Get Port Stat...

Page 197: ...0x2D 0x33 Get upgrade status 0x2C 0x2D 0x34 Activate firmware 0x2C 0x2D 0x35 Query self test results 0x2C 0x2D 0x36 Query rollback status 0x2C 0x2D 0x37 Initiate manual rollback 0x2C 0x2D 0x38 Table 8 19 Supported PICMG 3 0 Commands continued Command NetFn Request Response CMD The firmware upgrade commands supported by the blade are implemented according to the PICMG HPM 1 Revision 1 0 specificati...

Page 198: ...n the IPMC during runtime Before sending any of these commands the shelf management software must check whetherthereceivingIPMIcontrollersupportsArtesynEmbeddedTechnologiesspecific IPMIcommandsbyusingtheIPMIcommand GetDeviceID SendingArtesynEmbedded Technologies specific commands to IPMI controllers which do not support these IPMI commands will lead to no or undefined results Proper handling of th...

Page 199: ...ssignments on page 200 5 Feature Configuration 00h disabled Feature Selector E2h 01h enabled Feature Selector E2h Default 02h FFh reserved 6 Persistency Duration 00h volatile Actual duration depends on implementation 01h FFh reserved Response Data 1 Completion Code Generic plus the following command specific completion codes 80h feature selector not supported 81h feature configuration not supporte...

Page 200: ...t 5 Feature Configuration 6 Persistency Duration Table 8 23 Feature Selector Assignments Feature Selector Description E2h Boot Firmware Automatic Switchover Function Enable Disable Table 8 22 Get Feature Configuration Command continued Byte Data Field Table 8 24 Serial Output Commands Command Name NetFn Request Response CMD Description Set Serial Output 0x2E 0x2F 0x15 SeeSetSerialOutputCommandonpa...

Page 201: ...to determine which serial output source goes to a particular serial port connector Table 8 25 Set Serial Output Command Byte Data Field Request Data 1 3 Artesyn IANA Number 0065CDh LSB first 4 Serial connector type 0 Front panel connector 1 Backplane connector All other values are reserved 5 Serial connector instance number a value of 00h shall be used all other values are reserved 6 Serial output...

Page 202: ...esyn IANA Number 0065CDh LSB first 4 Serial connector type 0 Front panel connector 1 Backplane connector All other values are reserved 5 Serial connector instance number A value of 00h shall be used all other values are reserved Response Data 1 Completion code 2 4 Artesyn IANA Number 0065CDh LSB first 5 Serial output selector 0 payload interface All other values are reserved Table 8 27 OME Set Get...

Page 203: ...alue of 65h shall be used 3 MSB of Artesyn IANA Enterprise Number A value of 00h shall be used 4 ACPI System Power State to set Powerstatesaremutuallyexclusive Onlyonestatecanbesetat a time 7 1b set system power state always with 1 6 1 Reserved 0 System Power State enumeration 00h set S0 working 01h set S3 typically equates to suspend to RAM Response Data 1 Completion Code Generic completion codes...

Page 204: ...r A value of 00h shall be used Response Data 1 Completion Code 2 LSB of Artesyn IANA Enterprise Number A value of CDh shall be used 3 2nd byte of Artesyn IANA Enterprise Number A value of 65h shall be used 4 MSB of Artesyn IANA Enterprise Number A value of 00h shall be used 5 ACPI System Power State 7 2 reserved 1 0 System Power State enumeration 00h set S0 working 01h set S3 typically equates to ...

Page 205: ... NSN IANA Enterprise Number A value of 2Ah shall be used 2 2nd byte of NSN IANA Enterprise Number A value of 6Fh shall be used 3 MSB of NSN IANA Enterprise Number A value of 00h shall be used 4 00h 0Fh FRU ID 0h for ACPI5 A 5 Power performance mode level 7 1 Reserved 0 Power State Mode Level 0h normal performance mode 1h reduced performance mode Response Data 1 Completion Code Generic completion c...

Page 206: ...of NSN IANA Enterprise Number A value of 00h shall be used 4 00h 0Fh FRU ID 0h for ACPI5 A Response Data 1 Completion Code 2 LSB of NSN IANA Enterprise Number A value of 2Ah shall be used 3 2ndbyteofNSNIANAEnterpriseNumber Avalueof6Fhshallbe used 4 MSB of NSN IANA Enterprise Number A value of 00h shall be used 5 Power performance mode 7 1 Reserved 0 Power State Mode Level 0h normal performance mod...

Page 207: ...Set Hardware Address Table 8 41 on page 215 0x2E 0x2F 0x06 Get Handle Switch Table 8 42 on page 216 0x2E 0x2F 0x07 Set Handle Switch Table 8 43 on page 217 0x2E 0x2F 0x08 Get Payload Communication Time Out Table 8 44 on page 217 0x2E 0x2F 0x09 Set Payload Communication Time Out Table 8 45 on page 218 0x2E 0x2F 0x0A Enable Payload Control Table 8 46 on page 219 0x2E 0x2F 0x0B Disable Payload Contro...

Page 208: ...nded for debugging purposes and or operation in a non ATCA environment In standalone mode the carrier IPMC automatically activates and deactivates the on carrier payload and modules whenever it does not violate any carrier limitations Manual standalone Manual standalone mode is equivalent to standalone mode with only one exception carrier IPMC control over the on carrier payload is automatically d...

Page 209: ...s detects a threshold crossing Bits 2 1 Mode The current IPMC modes are defined as 0 Normal 1 Standalone for a description refer to Table 8 34 2 Manual Standalone for a description refer to Table 8 34 Bit 0 Control If set to 0 the IPMC control over the payload is disabled 6 Bits 4 7 Metallic Bus 2 Events These bits indicate pending Metallic Bus 2 requests arrived from the shelf manager 0 Metallic ...

Page 210: ...ee Bits 0 3 Clock Bus 1 Events These bits indicate pending Clock Bus 1 requests arrived from the shelf manager 0 Clock Bus 1 Query 1 Clock Bus 1 Release 2 Clock Bus 1 Force 3 Clock Bus 1 Free 8 Bits 4 7 Reserved Bits 0 3 Clock Bus 3 Events These bits indicate pending Clock Bus 3 requests arrived from the shelf manager 0 Clock Bus 3 Query 1 Clock Bus 3 Release 2 Clock Bus 3 Force 3 Clock Bus 3 Free...

Page 211: ... Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Interface ID 0 Serial Debug Interface Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 B...

Page 212: ... Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Interface ID 0 Serial Debug Interface 5 Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud Rate ID The baud rate ID defines the interface baud rate as follows 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps unsupported 4 115200 bps unsu...

Page 213: ... L Dump Enable If set to 1 the IPMC provides a trace of IPMB L messages that are arriving to going from the IPMC via IPMB L Bit 6 n a Bit 5 KCS Dump Enable Ifsetto 1 theIPMCprovidesatraceofKCSmessagesthat are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert...

Page 214: ...le If set to 1 the IPMC provides a trace of KCS messages that are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert Logging Enable If set to 1 the IPMC outputs important alert messages onto the serial debug interface Bit 1 Low level Error Logging Enable If s...

Page 215: ...d Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Hardware Address Table 8 41 Set Hardware Address Command Description Type Byte Data Field Request Data 1 3 PPS IANA Pri...

Page 216: ...B Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 41 Set Hardware Address Command Description continued Type Byte Data Field Table 8 42 Get Handle Switch Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A...

Page 217: ...0A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 44 Get Payload Communication Ti...

Page 218: ...ayload Communication Time Out Command Description continued Type Byte Data Field Table 8 45 Set Payload Communication Time Out Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Payload Time out Payload communication time out measured in hundreds of milliseconds Thus the payload...

Page 219: ...est Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 47 Disable Payload Control Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x0...

Page 220: ...ems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Reset Type Code 0x00 Cold IPMC reset to the current mode 0x01 Cold IPMC reset to the Normal mode 0x02 Cold IPMC reset to the Standalone mode for a description refer to Table 8 34 0x03 ColdIPMCresettotheManualStandalonemode for a description refer to Table 8 34 0x04 Reset the IPMC and enter Upgrade mode Response Data 1 Completion Code 2 4 PPS IANA ...

Page 221: ...ayload upon receiving the Graceful Reset command or time out If the IPMC participation is necessary the payload must request the IPMC to perform a payload reset The Graceful Reset command is also used to notify the IPMC about the completion of the payload shutdown sequence 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 49...

Page 222: ... the IPMC over the payload Interface to notify the IPMC that the payload shutdown is complete To avoid deadlocks that may occur if the payload software does not respond the IPMC provides a special time out for the payload shutdown sequence If the payload does not send the Graceful Reset command within a definite period of time the IPMC assumes that the payload shutdown sequence is finished and res...

Page 223: ...Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 5 Time Out measured in hundreds of milliseconds LSB first Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 53 Get Module State Command Description Type Byte Data Field Request Data 1 3 PPS IANA Pr...

Page 224: ... power is disabled 1 Management power is enabled Bit 3 0 Management power is bad 1 Management power is good Bit 4 0 Payload power is disabled 1 Payload power is enabled Bit 5 0 Payload power is bad 1 Payload power is good Bit 6 0 IPMB L buffer is not attached 1 IPMB L buffer is attached Bit 7 0 IPMB L buffer is not ready 1 IPMB L buffer is ready Table 8 53 Get Module State Command Description cont...

Page 225: ...ield Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Module Site ID Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Table 8 55 Disable Module Site Command Description Type Byte Data Field Request Data 1 3 PPS IANA Pri...

Page 226: ...ebuild the carrier SDR repository Table 8 56 Reset Carrier SDR Repository Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 ...

Page 227: ...t info area Product manufacturer EMERSON r Product name ATCA 7370 r Product part number DefinedbyArtesynNetworkPower Embedded Computing r Product serial number DefinedbyArtesynNetworkPower Embedded Computing r Multi record info area PICMG Blade Point To Point Connectivity Record Area This multi record area contains the ATCA blade Point to Point Connectivity Record according to PICMG 3 0 Rev 1 0 r ...

Page 228: ...n Dynamic power reconfiguration support No While the blade is powered it supports only one power level Dynamic power configuration No The power level is fixed and does not change Number of power draw levels 3 The amount of possible power levels Early Power Draw Levels Watt Complete early power level including IPMC Steady state Power Draw Levels Watt 1 120W 2 170W 3 200W Complete steady power consu...

Page 229: ...temperature sensors available on board Note OnthesingleprocessorvarianttheprocessoranditsDIMMsocketsarepopulatedonthe upper side of the board Components associated with the second processor are not populated on this product variant 9 3 Sensor Data Records The sensors available on the blades are detailed in the table below Figure 9 1 Block Diagram ...

Page 230: ...Description Assertion Deassertion Rearm 0 HS Carrier Hot Swap 0xF0 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 7 4 Cause 3 0 Previous State FRU ID 0x0 M0 0x1 M1 0x2 M2 0x3 M3 0x4 M4 0x5 M5 0x6 M6 0x7 M7 Asrt Auto 1 Hot Swap RTM Hot Swap 0xF0 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 7 4 Cause 3 0 Previous State FRU ID 0x0 M0 0x1 M1 0x2 M2 0x3 M3 0x4 M4 0x5 M5 ...

Page 231: ...p Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 6 Input Power Other Units based Sensor 0x0B Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto Table 9 3 Sensor Data Records continued Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Event Data Byte 2 Event Data Byte 3 Event Threshold Description Assertion Deassertion Rearm ...

Page 232: ...nchor 1 Emerson Emerson Pwr Entry Module 2 DIG_EnableA 1 DIG_EnableB 0 Mcu_Fault All other bits are reserved 0x0 Pwr Entry Module Status Change detected Asrt Auto 8 Inlet Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 9 Outlet Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 10 Board Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc As...

Page 233: ...ss Auto 16 DDR 2 Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 17 DDR 3 Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 18 DDR 4 Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 19 12 0V Temp 0x01 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 20 3 3V Temp 0x01 Threshold 0x01 reading threshold unr uc ...

Page 234: ... threshold unr uc lnr lc Asrt Deass Auto 26 1 5V DDR3 Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 27 IPMB0 Link Physical IPMB 0 0xF1 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 7 4 Channel Number 3 0 Reserved reading 0x0 IPMB A disabled IPMB B disabled 0x1 IPMB A enabled IPMB B disabled 0x2 IPMB A disabled IPMB B enabled 0x3 IPMB A enabled IPMB B enabled Asrt Deas...

Page 235: ...d 0x1 Hard Reset 0x2 Power Down 0x3 Power Cycle 0x8 Timer Interrupt Asrt Auto 29 IPMC POST Manageme nt Subsystem Health 0x28 digital Discrete 0x06 0x0 0x1 0xFF 0xFF 0x0 Performance Met 0x1 Performance Lags Asrt Auto Table 9 3 Sensor Data Records continued Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Event Data Byte 2 Event Data Byte 3 Event Threshold Description Asser...

Page 236: ...invalid hardware version 0x5 Entity contains invalid F W software 0x6 Hardware Change successful 0x7 Software or F W change successful Asrt Auto 31 FW Progress System Firmware Progress 0x0F Sensor specific discrete 0x6F 0x0 0x1 0x2 See IPMI Spec See IPMI Spec 0x0 System Firmware Error 0x1 System Firmware Hang 0x2 System Firmware Progress Asrt Auto Table 9 3 Sensor Data Records continued Sensor Num...

Page 237: ...completed 0x5 ROM boot completed 0x6 boot completed Asrt Auto 33 Boot Error Boot Error 0x1E Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0xFF 0xFF 0x0 No Bootable media 0x1 Non bootable diskette 0x2 PXE Server not found 0x3 Invalid boot sector 0x4 Timout waiting for user selection Asrt Auto Table 9 3 Sensor Data Records continued Sensor Number Sensor Name Sensor Type Event Reading Type Event ...

Page 238: ... boot 0x4 Automatic boot to diagnostic Asrt Auto 35 POST Code OEM 0xD1 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0xFF Readingaccording to EFI BIOS port80 status codes 0x0 BIOS POST Code 0x3 209 0x4 OEM 0xD1 0x6 0xFF 0x7 Reading according to EFI BIOS port80 status codes Asrt Auto Table 9 3 Sensor Data Records continued Sensor Number Sensor Name Sensor Type Event Reading Type Eve...

Page 239: ...Boot 0x6 Reserved Auto 37 Power Good Power Supply 0x08 Sensor specific discrete 0x6F 0x0 0x1 See IPMI Spec 0xFF 0x0 Presence detected 0x1 Power Supply Failure detected Asrt Auto 38 Boot Bank OEM 0xD2 Sensor specific discrete 0x6F 0x0 0xFF 0xFF 0x0 Boot Bank A Asrt Auto Table 9 3 Sensor Data Records continued Sensor Number Sensor Name Sensor Type Event Reading Type Event Data Byte 1 Event Data Byte...

Page 240: ...r on reset 7 2 Reserved 1 IPMC Pre Timout 0 IPMC Watchdog Timeout 0x0 Payload Reset detected Cause delivered in Event Byte 2 3 Asrt Auto 40 CPU Status Processor 0x07 Sensor specific discrete 0x6F 0x1 0xA 0xFF 0xFF 0x1 Thermal Trip 0xA ProcHot Asrt Auto 41 ACPI State System ACPI Power State 0x22 Sensor specific discrete 0x6F 0x0 0x3 0x5 0xFF 0xFF 0x0 S0 0x3 S3 0x5 S5 Asrt Auto Table 9 3 Sensor Data...

Page 241: ...System modified Ipmitool 10 1 2 Installing the ipmitool Refer Installing the ipmitool on page 175 for installing the ipmitool procedure 10 1 2 1 Update Procedure The Ipmitool HPM update requires two steps for an update 1 Upgrade the component Example ipmitool hpm upgrade file 2 Activate the component Example ipmitool hpm activate Both steps can also be integrated into one command ipmitool hpm upgr...

Page 242: ...us and allows remote firmware upgrade The count of the simultaneous upgrades is limited because of the bus speed Example from shelf manger Prompt ipmitool t 0x92 hpm upgrade file Example with RMCP Prompt ipmitool I lan H 192 168 34 8 U Administrator P Administrator t 0x92 hpm upgrade file 10 1 3 3 IPMI Over LAN BASE The IPMI over LAN interface uses the BASE Ethernet controller to do firmware upgra...

Page 243: ...irmware in the flash depending on the current value of the special partition status byte that is stored in the internal IPMC EEPROM The boot loader can fall back to the backup copy by booting the alternate partition The boot loader manages both active and backup firmware partitions It is responsible for detecting if the active firmware is invalid or has failed In either case the Boot loader will s...

Page 244: ...n be activated with a payload power cycle if you upgraded the firmware with activate option Payload always has access to the active boot bank and the IPMC always has access to the inactive boot bank All HPM 1 commands are directed to the inactive boot bank this includes get component properties The following figure shows the connection of the SPI busses whichareswitchedwith SetSystemBootOptions Bo...

Page 245: ...de Package The HPM upgrade package for this release contains the following files Table 10 1 HPM Upgrade Package Filename Description atca7370_em_bios_xx_yy_zzzz hpm Contains BIOS HPM 1 image with version xx_yy_zzzz atca7370_em_fpga_xx_yy_zzzz hpm Contains FPGA HPM 1 image with version xx_yy_zzzz atca7370_em_ibbl_ xx_yy_zzzz hpm Contains IPMC boot loader image with version xx_yy_zzzz atca7370_em_ip...

Page 246: ...Firmware Upgrade ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 246 ...

Page 247: ... or lits when the latch is closed The console redirection does not display BIOS POST The BIOS output does not include the expected data The blade does not answer to ping There is an IPMI alarm The embedded software in the hardware units is not consistent with the product release Verify the software is consistent with the product release The blade is not properly seated Make sure that the blade is ...

Page 248: ...Troubleshooting ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 248 ...

Page 249: ...r 3 In the Search text box type the product name and click GO B 2 Related Specifications For additional information refer to the following table for related specifications As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table B 1 Artesyn Embedded Technologies Embedded Comp...

Page 250: ...Related Documentation ATCA 7370 ATCA 7370 S Installation and Use 6806800P54G 250 ...

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Page 252: ...esyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2014 Artesyn Embedded Technologies Inc ...

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